Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T33
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	793632066	32004	0	0
CgEnOn_A	793632066	22759	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793632066	32004	0	0
T1	1921867	119	0	0
T2	1241191	3	0	0
T5	17896	10	0	0
T6	92061	9	0	0
T7	32966	3	0	0
T18	14581	7	0	0
T21	0	3	0	0
T25	78003	11	0	0
T26	125791	3	0	0
T27	11675	3	0	0
T28	146447	13	0	0
T40	7364	0	0	0
T44	35346	25	0	0
T45	6621	5	0	0
T46	0	5	0	0
T47	0	10	0	0
T81	0	5	0	0
T82	0	5	0	0
T156	35086	0	0	0
T161	40567	0	0	0
T162	3146453	0	0	0
T163	34528	0	0	0
T164	16530	0	0	0
T165	6413	0	0	0
T166	16298	0	0	0
T183	0	10	0	0
T184	0	15	0	0
T185	0	15	0	0
T186	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	793632066	22759	0	0
T1	821169	60	0	0
T2	539970	0	0	0
T4	259497	0	0	0
T5	2915	0	0	0
T11	0	27	0	0
T13	0	47	0	0
T18	6292	2	0	0
T19	4692	0	0	0
T20	6838	0	0	0
T21	6342	0	0	0
T22	7257	2	0	0
T23	11657	12	0	0
T24	57841	0	0	0
T33	0	32	0	0
T40	3339	0	0	0
T44	16204	25	0	0
T45	3067	5	0	0
T46	0	5	0	0
T47	0	10	0	0
T81	0	4	0	0
T82	0	4	0	0
T88	0	2	0	0
T104	0	2	0	0
T156	16243	0	0	0
T161	19909	0	0	0
T162	1302559	0	0	0
T163	16117	0	0	0
T164	7669	0	0	0
T165	2961	0	0	0
T166	7765	0	0	0
T183	0	10	0	0
T184	0	15	0	0
T185	0	15	0	0
T186	0	10	0	0
T187	0	5	0	0
T190	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T33
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	32976212	155	0	0
CgEnOn_A	32976212	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32976212	155	0	0
T40	712	0	0	0
T44	3595	5	0	0
T45	664	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T156	3580	0	0	0
T161	4767	0	0	0
T162	289411	0	0	0
T163	3595	0	0	0
T164	1696	0	0	0
T165	649	0	0	0
T166	1785	0	0	0
T183	0	2	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32976212	155	0	0
T40	712	0	0	0
T44	3595	5	0	0
T45	664	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T156	3580	0	0	0
T161	4767	0	0	0
T162	289411	0	0	0
T163	3595	0	0	0
T164	1696	0	0	0
T165	649	0	0	0
T166	1785	0	0	0
T183	0	2	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T33
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	16487696	155	0	0
CgEnOn_A	16487696	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16487696	155	0	0
T40	356	0	0	0
T44	1798	5	0	0
T45	332	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T156	1790	0	0	0
T161	2382	0	0	0
T162	144704	0	0	0
T163	1798	0	0	0
T164	848	0	0	0
T165	325	0	0	0
T166	892	0	0	0
T183	0	2	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16487696	155	0	0
T40	356	0	0	0
T44	1798	5	0	0
T45	332	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T156	1790	0	0	0
T161	2382	0	0	0
T162	144704	0	0	0
T163	1798	0	0	0
T164	848	0	0	0
T165	325	0	0	0
T166	892	0	0	0
T183	0	2	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T33
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	16487696	155	0	0
CgEnOn_A	16487696	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16487696	155	0	0
T40	356	0	0	0
T44	1798	5	0	0
T45	332	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T156	1790	0	0	0
T161	2382	0	0	0
T162	144704	0	0	0
T163	1798	0	0	0
T164	848	0	0	0
T165	325	0	0	0
T166	892	0	0	0
T183	0	2	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16487696	155	0	0
T40	356	0	0	0
T44	1798	5	0	0
T45	332	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T156	1790	0	0	0
T161	2382	0	0	0
T162	144704	0	0	0
T163	1798	0	0	0
T164	848	0	0	0
T165	325	0	0	0
T166	892	0	0	0
T183	0	2	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T33
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	16487696	155	0	0
CgEnOn_A	16487696	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16487696	155	0	0
T40	356	0	0	0
T44	1798	5	0	0
T45	332	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T156	1790	0	0	0
T161	2382	0	0	0
T162	144704	0	0	0
T163	1798	0	0	0
T164	848	0	0	0
T165	325	0	0	0
T166	892	0	0	0
T183	0	2	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16487696	155	0	0
T40	356	0	0	0
T44	1798	5	0	0
T45	332	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T156	1790	0	0	0
T161	2382	0	0	0
T162	144704	0	0	0
T163	1798	0	0	0
T164	848	0	0	0
T165	325	0	0	0
T166	892	0	0	0
T183	0	2	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T33
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	67807234	155	0	0
CgEnOn_A	67807234	140	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67807234	155	0	0
T40	1559	0	0	0
T44	7215	5	0	0
T45	1407	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T156	7293	0	0	0
T161	7996	0	0	0
T162	579036	0	0	0
T163	7128	0	0	0
T164	3429	0	0	0
T165	1337	0	0	0
T166	3304	0	0	0
T183	0	2	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67807234	140	0	0
T40	1559	0	0	0
T44	7215	5	0	0
T45	1407	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T156	7293	0	0	0
T161	7996	0	0	0
T162	579036	0	0	0
T163	7128	0	0	0
T164	3429	0	0	0
T165	1337	0	0	0
T166	3304	0	0	0
T183	0	2	0	0
T184	0	3	0	0
T185	0	3	0	0
T186	0	2	0	0
T187	0	5	0	0
T188	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T33
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	75574951	158	0	0
CgEnOn_A	75574951	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75574951	158	0	0
T40	1623	0	0	0
T44	7839	4	0	0
T45	1433	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T156	7598	0	0	0
T161	8330	0	0	0
T162	741181	0	0	0
T163	7424	0	0	0
T164	3573	0	0	0
T165	1392	0	0	0
T166	3441	0	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	2	0	0
T185	0	6	0	0
T186	0	1	0	0
T187	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75574951	153	0	0
T40	1623	0	0	0
T44	7839	4	0	0
T45	1433	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T156	7598	0	0	0
T161	8330	0	0	0
T162	741181	0	0	0
T163	7424	0	0	0
T164	3573	0	0	0
T165	1392	0	0	0
T166	3441	0	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	2	0	0
T185	0	6	0	0
T186	0	1	0	0
T187	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T33
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	75574951	158	0	0
CgEnOn_A	75574951	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75574951	158	0	0
T40	1623	0	0	0
T44	7839	4	0	0
T45	1433	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T156	7598	0	0	0
T161	8330	0	0	0
T162	741181	0	0	0
T163	7424	0	0	0
T164	3573	0	0	0
T165	1392	0	0	0
T166	3441	0	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	2	0	0
T185	0	6	0	0
T186	0	1	0	0
T187	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75574951	153	0	0
T40	1623	0	0	0
T44	7839	4	0	0
T45	1433	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T156	7598	0	0	0
T161	8330	0	0	0
T162	741181	0	0	0
T163	7424	0	0	0
T164	3573	0	0	0
T165	1392	0	0	0
T166	3441	0	0	0
T182	0	2	0	0
T183	0	3	0	0
T184	0	2	0	0
T185	0	6	0	0
T186	0	1	0	0
T187	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T33
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	36332342	149	0	0
CgEnOn_A	36332342	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36332342	149	0	0
T40	779	0	0	0
T44	3464	4	0	0
T45	688	1	0	0
T47	0	2	0	0
T156	3647	0	0	0
T161	3998	0	0	0
T162	361532	0	0	0
T163	3563	0	0	0
T164	1715	0	0	0
T165	668	0	0	0
T166	1651	0	0	0
T183	0	4	0	0
T184	0	2	0	0
T185	0	6	0	0
T186	0	2	0	0
T187	0	6	0	0
T188	0	6	0	0
T189	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36332342	147	0	0
T40	779	0	0	0
T44	3464	4	0	0
T45	688	1	0	0
T47	0	2	0	0
T156	3647	0	0	0
T161	3998	0	0	0
T162	361532	0	0	0
T163	3563	0	0	0
T164	1715	0	0	0
T165	668	0	0	0
T166	1651	0	0	0
T183	0	4	0	0
T184	0	2	0	0
T185	0	6	0	0
T186	0	2	0	0
T187	0	6	0	0
T188	0	6	0	0
T189	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	16487696	5413	0	0
CgEnOn_A	16487696	3121	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16487696	5413	0	0
T1	70920	37	0	0
T2	48345	1	0	0
T5	680	1	0	0
T6	3560	1	0	0
T7	1270	1	0	0
T18	541	2	0	0
T25	3015	1	0	0
T26	8368	1	0	0
T27	441	1	0	0
T28	5682	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16487696	3121	0	0
T1	70920	31	0	0
T2	48345	0	0	0
T4	37058	0	0	0
T11	0	13	0	0
T13	0	22	0	0
T18	541	1	0	0
T19	711	0	0	0
T20	993	0	0	0
T21	895	0	0	0
T22	1025	1	0	0
T23	1656	6	0	0
T24	8256	0	0	0
T33	0	17	0	0
T88	0	1	0	0
T104	0	1	0	0
T190	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	32976212	5385	0	0
CgEnOn_A	32976212	3093	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32976212	5385	0	0
T1	141846	35	0	0
T2	96691	1	0	0
T5	1359	1	0	0
T6	7120	1	0	0
T7	2539	1	0	0
T18	1083	2	0	0
T25	6031	1	0	0
T26	16735	1	0	0
T27	882	1	0	0
T28	11364	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	32976212	3093	0	0
T1	141846	29	0	0
T2	96691	0	0	0
T4	74115	0	0	0
T11	0	14	0	0
T13	0	25	0	0
T18	1083	1	0	0
T19	1423	0	0	0
T20	1988	0	0	0
T21	1789	0	0	0
T22	2051	1	0	0
T23	3312	6	0	0
T24	16511	0	0	0
T33	0	15	0	0
T88	0	1	0	0
T104	0	1	0	0
T190	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	67807234	5447	0	0
CgEnOn_A	67807234	3140	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67807234	5447	0	0
T1	292111	35	0	0
T2	193434	1	0	0
T5	2798	1	0	0
T6	14361	1	0	0
T7	5145	1	0	0
T18	2286	2	0	0
T25	12169	1	0	0
T26	17768	1	0	0
T27	1827	1	0	0
T28	22835	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67807234	3140	0	0
T1	292111	29	0	0
T2	193434	0	0	0
T4	148324	0	0	0
T11	0	14	0	0
T13	0	25	0	0
T18	2286	1	0	0
T19	2558	0	0	0
T20	3857	0	0	0
T21	3658	0	0	0
T22	4181	1	0	0
T23	6689	6	0	0
T24	33074	0	0	0
T33	0	17	0	0
T88	0	1	0	0
T104	0	1	0	0
T190	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T47
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	36332342	5425	0	0
CgEnOn_A	36332342	3118	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36332342	5425	0	0
T1	151822	35	0	0
T2	96721	1	0	0
T5	1399	1	0	0
T6	7180	1	0	0
T7	2572	1	0	0
T18	1143	2	0	0
T25	6084	1	0	0
T26	8884	1	0	0
T27	913	1	0	0
T28	11418	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36332342	3118	0	0
T1	151822	29	0	0
T2	96721	0	0	0
T4	85686	0	0	0
T11	0	14	0	0
T13	0	21	0	0
T18	1143	1	0	0
T19	1279	0	0	0
T20	1928	0	0	0
T21	1829	0	0	0
T22	2090	1	0	0
T23	3345	7	0	0
T24	16538	0	0	0
T33	0	15	0	0
T88	0	1	0	0
T104	0	1	0	0
T190	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T33
1	0	Covered	T5,T6,T25
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	75574951	2285	0	0
CgEnOn_A	75574951	2280	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75574951	2285	0	0
T1	316292	12	0	0
T2	201500	0	0	0
T5	2915	7	0	0
T6	14960	6	0	0
T7	5360	0	0	0
T18	2382	1	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	0	2	0	0
T25	12676	8	0	0
T26	18509	0	0	0
T27	1903	0	0	0
T28	23787	10	0	0
T33	0	28	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75574951	2280	0	0
T1	316292	12	0	0
T2	201500	0	0	0
T5	2915	7	0	0
T6	14960	6	0	0
T7	5360	0	0	0
T18	2382	1	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	0	2	0	0
T25	12676	8	0	0
T26	18509	0	0	0
T27	1903	0	0	0
T28	23787	10	0	0
T33	0	28	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T33
1	0	Covered	T5,T6,T25
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	75574951	2294	0	0
CgEnOn_A	75574951	2289	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75574951	2294	0	0
T1	316292	12	0	0
T2	201500	0	0	0
T5	2915	6	0	0
T6	14960	4	0	0
T7	5360	0	0	0
T18	2382	1	0	0
T21	0	4	0	0
T22	0	1	0	0
T24	0	6	0	0
T25	12676	9	0	0
T26	18509	0	0	0
T27	1903	0	0	0
T28	23787	6	0	0
T33	0	29	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75574951	2289	0	0
T1	316292	12	0	0
T2	201500	0	0	0
T5	2915	6	0	0
T6	14960	4	0	0
T7	5360	0	0	0
T18	2382	1	0	0
T21	0	4	0	0
T22	0	1	0	0
T24	0	6	0	0
T25	12676	9	0	0
T26	18509	0	0	0
T27	1903	0	0	0
T28	23787	6	0	0
T33	0	29	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T33
1	0	Covered	T5,T6,T25
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	75574951	2287	0	0
CgEnOn_A	75574951	2282	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75574951	2287	0	0
T1	316292	12	0	0
T2	201500	0	0	0
T5	2915	7	0	0
T6	14960	8	0	0
T7	5360	0	0	0
T18	2382	1	0	0
T21	0	5	0	0
T22	0	1	0	0
T24	0	1	0	0
T25	12676	7	0	0
T26	18509	0	0	0
T27	1903	0	0	0
T28	23787	7	0	0
T33	0	23	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75574951	2282	0	0
T1	316292	12	0	0
T2	201500	0	0	0
T5	2915	7	0	0
T6	14960	8	0	0
T7	5360	0	0	0
T18	2382	1	0	0
T21	0	5	0	0
T22	0	1	0	0
T24	0	1	0	0
T25	12676	7	0	0
T26	18509	0	0	0
T27	1903	0	0	0
T28	23787	7	0	0
T33	0	23	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T24,T33
1	0	Covered	T5,T6,T25
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	75574951	2228	0	0
CgEnOn_A	75574951	2223	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75574951	2228	0	0
T1	316292	12	0	0
T2	201500	0	0	0
T5	2915	6	0	0
T6	14960	5	0	0
T7	5360	0	0	0
T18	2382	1	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	0	7	0	0
T25	12676	6	0	0
T26	18509	0	0	0
T27	1903	0	0	0
T28	23787	7	0	0
T33	0	23	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75574951	2223	0	0
T1	316292	12	0	0
T2	201500	0	0	0
T5	2915	6	0	0
T6	14960	5	0	0
T7	5360	0	0	0
T18	2382	1	0	0
T21	0	3	0	0
T22	0	1	0	0
T24	0	7	0	0
T25	12676	6	0	0
T26	18509	0	0	0
T27	1903	0	0	0
T28	23787	7	0	0
T33	0	23	0	0