Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	223021	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

499525

1

T4

2

T5

15

T6

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	204227	1			T5	24		T6	1		T21	19
values[0x0]	246599	1			T4	2		T5	2		T6	2
values[0x1]	271720	1			T4	5		T5	16		T6	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154375	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

568171

1

T4

4

T5

19

T6

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3323	1			T1	66		T2	6		T3	30
valid_sources[0x01]	2930	1			T1	58		T3	66		T10	15
valid_sources[0x02]	3761	1			T1	47		T3	61		T22	1
valid_sources[0x03]	2835	1			T1	35		T3	63		T9	3
valid_sources[0x04]	2977	1			T1	17		T3	53		T26	1
valid_sources[0x05]	2233	1			T21	4		T1	17		T3	70
valid_sources[0x06]	2647	1			T1	48		T2	1		T3	57
valid_sources[0x07]	2847	1			T1	28		T2	1		T17	1
valid_sources[0x08]	2895	1			T1	37		T2	2		T3	38
valid_sources[0x09]	2275	1			T1	41		T2	1		T3	51
valid_sources[0x0a]	2704	1			T1	38		T2	1		T3	55
valid_sources[0x0b]	2535	1			T1	30		T2	4		T3	65
valid_sources[0x0c]	2315	1			T1	59		T3	58		T9	1
valid_sources[0x0d]	2953	1			T1	14		T2	2		T3	44
valid_sources[0x0e]	2778	1			T1	24		T3	66		T9	1
valid_sources[0x0f]	2462	1			T21	4		T1	41		T2	1
valid_sources[0x10]	2470	1			T21	1		T1	56		T16	2
valid_sources[0x11]	2428	1			T1	37		T2	2		T3	50
valid_sources[0x12]	2671	1			T5	2		T21	3		T1	40
valid_sources[0x13]	2700	1			T1	50		T3	53		T20	1
valid_sources[0x14]	2432	1			T1	42		T2	1		T3	57
valid_sources[0x15]	2507	1			T1	45		T2	2		T3	64
valid_sources[0x16]	4323	1			T1	32		T2	1		T3	48
valid_sources[0x17]	2735	1			T1	25		T2	1		T3	45
valid_sources[0x18]	3030	1			T1	49		T3	48		T9	1
valid_sources[0x19]	2587	1			T1	50		T2	1		T3	52
valid_sources[0x1a]	2685	1			T21	6		T1	29		T3	53
valid_sources[0x1b]	3525	1			T1	28		T3	43		T10	37
valid_sources[0x1c]	2778	1			T1	33		T3	52		T9	3
valid_sources[0x1d]	3043	1			T1	66		T16	1		T2	1
valid_sources[0x1e]	2427	1			T1	33		T2	1		T3	59
valid_sources[0x1f]	3118	1			T1	53		T3	51		T9	1
valid_sources[0x20]	2607	1			T1	34		T2	2		T3	32
valid_sources[0x21]	3652	1			T1	33		T2	1		T3	53
valid_sources[0x22]	2768	1			T1	32		T16	2		T2	1
valid_sources[0x23]	2529	1			T1	56		T3	42		T26	1
valid_sources[0x24]	2524	1			T1	54		T2	8		T3	53
valid_sources[0x25]	2885	1			T1	33		T2	1		T3	55
valid_sources[0x26]	3070	1			T1	47		T3	55		T10	67
valid_sources[0x27]	2859	1			T21	6		T1	23		T2	2
valid_sources[0x28]	3120	1			T1	53		T2	1		T3	59
valid_sources[0x29]	2752	1			T1	57		T3	55		T9	2
valid_sources[0x2a]	5019	1			T1	42		T16	1		T2	1
valid_sources[0x2b]	3069	1			T1	46		T3	53		T9	1
valid_sources[0x2c]	2297	1			T1	47		T2	2		T3	43
valid_sources[0x2d]	2577	1			T1	45		T17	1		T3	68
valid_sources[0x2e]	2284	1			T1	35		T2	2		T3	41
valid_sources[0x2f]	2933	1			T1	53		T2	2		T3	46
valid_sources[0x30]	2618	1			T1	59		T16	1		T3	60
valid_sources[0x31]	2861	1			T1	45		T2	2		T3	84
valid_sources[0x32]	2820	1			T5	1		T1	37		T3	54
valid_sources[0x33]	2734	1			T1	49		T3	54		T9	1
valid_sources[0x34]	2565	1			T1	35		T3	48		T22	1
valid_sources[0x35]	3013	1			T1	34		T3	58		T11	72
valid_sources[0x36]	2860	1			T1	60		T16	1		T3	49
valid_sources[0x37]	2834	1			T1	29		T3	56		T9	1
valid_sources[0x38]	2794	1			T1	32		T2	3		T3	60
valid_sources[0x39]	2466	1			T1	30		T2	2		T3	53
valid_sources[0x3a]	2423	1			T1	49		T3	50		T9	2
valid_sources[0x3b]	2764	1			T1	74		T16	1		T2	1
valid_sources[0x3c]	3334	1			T1	25		T2	7		T3	44
valid_sources[0x3d]	2577	1			T1	50		T3	59		T9	1
valid_sources[0x3e]	2801	1			T1	30		T3	54		T20	1
valid_sources[0x3f]	2703	1			T1	44		T2	1		T3	45
valid_sources[0x40]	2926	1			T1	71		T3	49		T9	1
valid_sources[0x41]	3121	1			T1	57		T3	59		T9	1
valid_sources[0x42]	2731	1			T1	42		T16	1		T2	1
valid_sources[0x43]	2586	1			T1	63		T2	2		T3	65
valid_sources[0x44]	2972	1			T1	40		T3	50		T9	1
valid_sources[0x45]	3614	1			T1	71		T2	1		T3	44
valid_sources[0x46]	2203	1			T1	44		T2	2		T3	52
valid_sources[0x47]	2861	1			T1	28		T3	59		T9	1
valid_sources[0x48]	2517	1			T21	7		T1	46		T2	2
valid_sources[0x49]	2986	1			T1	64		T3	67		T20	1
valid_sources[0x4a]	2530	1			T1	28		T3	62		T9	2
valid_sources[0x4b]	2203	1			T1	56		T2	2		T3	53
valid_sources[0x4c]	2267	1			T1	34		T2	2		T3	48
valid_sources[0x4d]	2680	1			T1	40		T2	1		T3	57
valid_sources[0x4e]	2453	1			T1	37		T3	57		T9	2
valid_sources[0x4f]	2419	1			T1	34		T3	53		T9	2
valid_sources[0x50]	2730	1			T1	28		T2	3		T3	59
valid_sources[0x51]	2880	1			T1	56		T2	1		T3	63
valid_sources[0x52]	2553	1			T1	25		T2	1		T3	39
valid_sources[0x53]	2560	1			T1	51		T3	53		T9	1
valid_sources[0x54]	2767	1			T1	52		T3	59		T10	4
valid_sources[0x55]	2685	1			T1	62		T2	1		T3	49
valid_sources[0x56]	3326	1			T1	42		T2	1		T3	51
valid_sources[0x57]	2984	1			T1	45		T2	2		T3	54
valid_sources[0x58]	2642	1			T1	37		T2	1		T3	61
valid_sources[0x59]	3573	1			T1	51		T3	55		T10	25
valid_sources[0x5a]	3058	1			T5	3		T1	67		T2	2
valid_sources[0x5b]	3328	1			T1	59		T3	61		T9	1
valid_sources[0x5c]	2633	1			T1	56		T2	1		T3	63
valid_sources[0x5d]	2604	1			T1	42		T2	2		T3	56
valid_sources[0x5e]	2677	1			T1	24		T3	52		T11	57
valid_sources[0x5f]	2482	1			T1	55		T2	1		T3	40
valid_sources[0x60]	2957	1			T1	42		T2	1		T3	63
valid_sources[0x61]	3049	1			T1	24		T2	2		T3	76
valid_sources[0x62]	2656	1			T1	67		T2	3		T3	41
valid_sources[0x63]	2396	1			T1	53		T2	3		T3	55
valid_sources[0x64]	2464	1			T1	28		T3	38		T9	1
valid_sources[0x65]	2641	1			T1	32		T3	39		T20	1
valid_sources[0x66]	3117	1			T1	43		T16	4		T2	1
valid_sources[0x67]	2579	1			T1	35		T2	1		T3	59
valid_sources[0x68]	3279	1			T1	32		T2	2		T3	71
valid_sources[0x69]	2625	1			T1	32		T3	67		T9	1
valid_sources[0x6a]	2303	1			T1	34		T2	3		T3	43
valid_sources[0x6b]	3081	1			T5	8		T6	1		T1	39
valid_sources[0x6c]	2809	1			T1	50		T3	57		T9	2
valid_sources[0x6d]	2777	1			T1	56		T2	1		T3	49
valid_sources[0x6e]	3079	1			T1	59		T2	1		T3	49
valid_sources[0x6f]	2406	1			T1	48		T2	2		T3	55
valid_sources[0x70]	2850	1			T1	43		T2	3		T3	52
valid_sources[0x71]	2577	1			T1	28		T2	2		T3	48
valid_sources[0x72]	3076	1			T1	42		T2	1		T3	41
valid_sources[0x73]	2891	1			T1	47		T2	3		T3	48
valid_sources[0x74]	2797	1			T1	20		T2	3		T3	59
valid_sources[0x75]	2652	1			T1	51		T2	1		T3	65
valid_sources[0x76]	3221	1			T1	29		T2	1		T3	50
valid_sources[0x77]	2527	1			T1	48		T3	45		T9	1
valid_sources[0x78]	3269	1			T1	41		T3	42		T9	1
valid_sources[0x79]	2698	1			T1	40		T16	1		T2	1
valid_sources[0x7a]	2670	1			T1	36		T3	47		T22	1
valid_sources[0x7b]	2936	1			T1	44		T3	75		T10	60
valid_sources[0x7c]	2754	1			T1	47		T2	4		T3	40
valid_sources[0x7d]	2943	1			T1	35		T3	67		T9	1
valid_sources[0x7e]	2532	1			T1	43		T2	3		T3	46
valid_sources[0x7f]	3055	1			T1	44		T3	58		T9	1
valid_sources[0x80]	2591	1			T1	26		T3	50		T9	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

136593

1

T5

10

T21

10

T1

2423

values[0x0]

all_enables

biggest_size

195827

1

T4

2

T5

1

T6

1

values[0x1]

all_enables

biggest_size

167105

1

T5

4

T6

1

T21

4