Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T18
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T18,T31,T32
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	233113296	8346	0	0
GateOpen_A	233113296	15063	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233113296	8346	0	0
T1	816154	127	0	0
T2	327155	0	0	0
T3	0	73	0	0
T4	7586	5	0	0
T5	4128	0	0	0
T6	18609	0	0	0
T10	0	38	0	0
T11	0	155	0	0
T14	0	75	0	0
T16	4439	0	0	0
T17	4699	0	0	0
T18	5645	19	0	0
T19	14796	0	0	0
T21	16992	0	0	0
T31	0	7	0	0
T133	0	17	0	0
T156	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233113296	15063	0	0
T1	816154	156	0	0
T2	327155	0	0	0
T3	0	90	0	0
T4	7586	9	0	0
T5	4128	4	0	0
T6	18609	4	0	0
T9	0	4	0	0
T10	0	46	0	0
T16	4439	0	0	0
T17	4699	4	0	0
T18	5645	23	0	0
T19	14796	4	0	0
T21	16992	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T18
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T18,T31,T32
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	25282501	2020	0	0
GateOpen_A	25282501	3694	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25282501	2020	0	0
T1	88066	30	0	0
T2	36323	0	0	0
T3	0	17	0	0
T4	839	1	0	0
T5	439	0	0	0
T6	2148	0	0	0
T10	0	9	0	0
T11	0	34	0	0
T14	0	18	0	0
T16	527	0	0	0
T17	518	0	0	0
T18	618	5	0	0
T19	1633	0	0	0
T21	1989	0	0	0
T31	0	2	0	0
T133	0	3	0	0
T156	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25282501	3694	0	0
T1	88066	37	0	0
T2	36323	0	0	0
T3	0	21	0	0
T4	839	2	0	0
T5	439	1	0	0
T6	2148	1	0	0
T9	0	1	0	0
T10	0	11	0	0
T16	527	0	0	0
T17	518	1	0	0
T18	618	6	0	0
T19	1633	1	0	0
T21	1989	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T18
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T18,T31,T32
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	50565538	2108	0	0
GateOpen_A	50565538	3783	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50565538	2108	0	0
T1	176140	33	0	0
T2	72647	0	0	0
T3	0	20	0	0
T4	1678	1	0	0
T5	877	0	0	0
T6	4295	0	0	0
T10	0	10	0	0
T11	0	41	0	0
T14	0	20	0	0
T16	1058	0	0	0
T17	1036	0	0	0
T18	1235	5	0	0
T19	3266	0	0	0
T21	3979	0	0	0
T31	0	2	0	0
T133	0	5	0	0
T156	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50565538	3783	0	0
T1	176140	40	0	0
T2	72647	0	0	0
T3	0	24	0	0
T4	1678	2	0	0
T5	877	1	0	0
T6	4295	1	0	0
T9	0	1	0	0
T10	0	12	0	0
T16	1058	0	0	0
T17	1036	1	0	0
T18	1235	6	0	0
T19	3266	1	0	0
T21	3979	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T18
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T18,T31,T32
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	103026237	2126	0	0
GateOpen_A	103026237	3809	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103026237	2126	0	0
T1	362589	33	0	0
T2	145455	0	0	0
T3	0	19	0	0
T4	3379	2	0	0
T5	1875	0	0	0
T6	8110	0	0	0
T10	0	9	0	0
T11	0	39	0	0
T14	0	21	0	0
T16	1903	0	0	0
T17	2097	0	0	0
T18	2550	5	0	0
T19	6598	0	0	0
T21	7349	0	0	0
T31	0	2	0	0
T133	0	5	0	0
T156	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103026237	3809	0	0
T1	362589	40	0	0
T2	145455	0	0	0
T3	0	23	0	0
T4	3379	3	0	0
T5	1875	1	0	0
T6	8110	1	0	0
T9	0	1	0	0
T10	0	11	0	0
T16	1903	0	0	0
T17	2097	1	0	0
T18	2550	6	0	0
T19	6598	1	0	0
T21	7349	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T1,T18
0	1	Covered	T4,T1,T2
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T2
1	0	Covered	T18,T31,T32
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	54239020	2092	0	0
GateOpen_A	54239020	3777	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54239020	2092	0	0
T1	189359	31	0	0
T2	72730	0	0	0
T3	0	17	0	0
T4	1690	1	0	0
T5	937	0	0	0
T6	4056	0	0	0
T10	0	10	0	0
T11	0	41	0	0
T14	0	16	0	0
T16	951	0	0	0
T17	1048	0	0	0
T18	1242	4	0	0
T19	3299	0	0	0
T21	3675	0	0	0
T31	0	1	0	0
T133	0	4	0	0
T156	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54239020	3777	0	0
T1	189359	39	0	0
T2	72730	0	0	0
T3	0	22	0	0
T4	1690	2	0	0
T5	937	1	0	0
T6	4056	1	0	0
T9	0	1	0	0
T10	0	12	0	0
T16	951	0	0	0
T17	1048	1	0	0
T18	1242	5	0	0
T19	3299	1	0	0
T21	3675	0	0	0