Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	200763560	39647	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200763560	39647	0	0
T1	1972455	395	0	0
T2	181815	50	0	0
T3	1625480	434	0	0
T9	128925	100	0	0
T10	1587550	849	0	0
T11	0	418	0	0
T12	0	144	0	0
T13	0	99	0	0
T14	0	107	0	0
T15	0	608	0	0
T16	9900	0	0	0
T17	5350	0	0	0
T18	7140	0	0	0
T19	3780	0	0	0
T20	9720	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	40152712	6037	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	6037	0	0
T1	394491	50	0	0
T2	36363	8	0	0
T3	325096	56	0	0
T9	25785	16	0	0
T10	317510	125	0	0
T11	0	67	0	0
T12	0	26	0	0
T13	0	16	0	0
T14	0	21	0	0
T15	0	78	0	0
T16	1980	0	0	0
T17	1070	0	0	0
T18	1428	0	0	0
T19	756	0	0	0
T20	1944	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	40152712	5975	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	5975	0	0
T1	394491	58	0	0
T2	36363	8	0	0
T3	325096	63	0	0
T9	25785	16	0	0
T10	317510	124	0	0
T11	0	67	0	0
T12	0	26	0	0
T13	0	16	0	0
T14	0	21	0	0
T15	0	87	0	0
T16	1980	0	0	0
T17	1070	0	0	0
T18	1428	0	0	0
T19	756	0	0	0
T20	1944	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	40152712	8001	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	8001	0	0
T1	394491	79	0	0
T2	36363	10	0	0
T3	325096	88	0	0
T9	25785	20	0	0
T10	317510	170	0	0
T11	0	85	0	0
T12	0	28	0	0
T13	0	20	0	0
T14	0	21	0	0
T15	0	122	0	0
T16	1980	0	0	0
T17	1070	0	0	0
T18	1428	0	0	0
T19	756	0	0	0
T20	1944	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	40152712	7969	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	7969	0	0
T1	394491	78	0	0
T2	36363	10	0	0
T3	325096	86	0	0
T9	25785	20	0	0
T10	317510	170	0	0
T11	0	85	0	0
T12	0	28	0	0
T13	0	20	0	0
T14	0	21	0	0
T15	0	119	0	0
T16	1980	0	0	0
T17	1070	0	0	0
T18	1428	0	0	0
T19	756	0	0	0
T20	1944	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	40152712	11665	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	11665	0	0
T1	394491	130	0	0
T2	36363	14	0	0
T3	325096	141	0	0
T9	25785	28	0	0
T10	317510	260	0	0
T11	0	114	0	0
T12	0	36	0	0
T13	0	27	0	0
T14	0	23	0	0
T15	0	202	0	0
T16	1980	0	0	0
T17	1070	0	0	0
T18	1428	0	0	0
T19	756	0	0	0
T20	1944	0	0	0