Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	40152712	37474496	0	0
AllClkBypReqTrue_A	40152712	92619	0	0
IoClkBypReqFalse_A	40152712	37412623	0	2415
IoClkBypReqTrue_A	40152712	149748	0	0
LcClkBypAckFalse_A	40152712	37480129	0	0
LcClkBypAckTrue_A	40152712	86986	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	37474496	0	0
T1	394491	356569	0	0
T2	36363	36274	0	0
T4	844	803	0	0
T5	1933	1666	0	0
T6	591	545	0	0
T16	1980	1707	0	0
T17	1070	1000	0	0
T18	1428	1364	0	0
T19	756	738	0	0
T21	1836	1625	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	92619	0	0
T1	394491	1744	0	0
T2	36363	0	0	0
T3	325096	774	0	0
T6	591	40	0	0
T9	25785	0	0	0
T10	0	189	0	0
T11	0	1960	0	0
T14	0	531	0	0
T16	1980	118	0	0
T17	1070	0	0	0
T18	1428	0	0	0
T19	756	0	0	0
T21	1836	163	0	0
T105	0	208	0	0
T106	0	198	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	37412623	0	2415
T1	394491	356045	0	3
T2	36363	36270	0	3
T4	844	801	0	3
T5	1933	1664	0	3
T6	591	550	0	3
T16	1980	1510	0	3
T17	1070	998	0	3
T18	1428	1362	0	3
T19	756	736	0	3
T21	1836	1576	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	149748	0	0
T1	394491	2246	0	0
T2	36363	0	0	0
T3	325096	1181	0	0
T6	591	33	0	0
T9	25785	0	0	0
T10	0	355	0	0
T11	0	2538	0	0
T16	1980	313	0	0
T17	1070	0	0	0
T18	1428	0	0	0
T19	756	0	0	0
T21	1836	210	0	0
T105	0	230	0	0
T106	0	344	0	0
T107	0	645	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	37480129	0	0
T1	394491	356916	0	0
T2	36363	36274	0	0
T4	844	803	0	0
T5	1933	1666	0	0
T6	591	556	0	0
T16	1980	1612	0	0
T17	1070	1000	0	0
T18	1428	1364	0	0
T19	756	738	0	0
T21	1836	1656	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	86986	0	0
T1	394491	1397	0	0
T2	36363	0	0	0
T3	325096	874	0	0
T6	591	29	0	0
T9	25785	0	0	0
T10	0	203	0	0
T11	0	1411	0	0
T16	1980	213	0	0
T17	1070	0	0	0
T18	1428	0	0	0
T19	756	0	0	0
T21	1836	132	0	0
T105	0	162	0	0
T106	0	232	0	0
T107	0	287	0	0