Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	451764256	9467	0	0
TransStop_A	451764256	4922	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451764256	9467	0	0
T1	1577968	170	0	0
T2	606076	0	0	0
T3	1276388	108	0	0
T5	7808	13	0	0
T6	33792	0	0	0
T10	0	38	0	0
T11	0	93	0	0
T14	0	112	0	0
T15	0	12	0	0
T16	7924	0	0	0
T17	8736	0	0	0
T18	10360	0	0	0
T19	27492	2	0	0
T20	0	30	0	0
T21	30616	0	0	0
T108	0	12	0	0
T109	0	12	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	451764256	4922	0	0
T1	1577968	88	0	0
T2	606076	0	0	0
T3	1276388	62	0	0
T5	5856	4	0	0
T6	25344	0	0	0
T9	107443	0	0	0
T10	617023	20	0	0
T11	0	55	0	0
T14	0	57	0	0
T15	0	4	0	0
T16	7924	0	0	0
T17	8736	0	0	0
T18	10360	0	0	0
T19	27492	2	0	0
T20	5721	17	0	0
T21	22962	0	0	0
T108	0	3	0	0
T109	0	13	0	0
T110	0	10	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	112941064	2401	0	0
TransStop_A	112941064	1266	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112941064	2401	0	0
T1	394492	46	0	0
T2	151519	0	0	0
T3	319097	29	0	0
T5	1952	5	0	0
T6	8448	0	0	0
T10	0	13	0	0
T11	0	26	0	0
T14	0	31	0	0
T15	0	3	0	0
T16	1981	0	0	0
T17	2184	0	0	0
T18	2590	0	0	0
T19	6873	1	0	0
T20	0	9	0	0
T21	7654	0	0	0
T108	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112941064	1266	0	0
T1	394492	23	0	0
T2	151519	0	0	0
T3	319097	16	0	0
T5	1952	2	0	0
T6	8448	0	0	0
T10	0	8	0	0
T11	0	15	0	0
T14	0	15	0	0
T15	0	1	0	0
T16	1981	0	0	0
T17	2184	0	0	0
T18	2590	0	0	0
T19	6873	1	0	0
T20	0	5	0	0
T21	7654	0	0	0
T108	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	112941064	2351	0	0
TransStop_A	112941064	1219	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112941064	2351	0	0
T1	394492	30	0	0
T2	151519	0	0	0
T3	319097	27	0	0
T5	1952	3	0	0
T6	8448	0	0	0
T10	0	9	0	0
T11	0	22	0	0
T14	0	29	0	0
T15	0	3	0	0
T16	1981	0	0	0
T17	2184	0	0	0
T18	2590	0	0	0
T19	6873	0	0	0
T20	0	4	0	0
T21	7654	0	0	0
T108	0	4	0	0
T109	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112941064	1219	0	0
T1	394492	16	0	0
T2	151519	0	0	0
T3	319097	15	0	0
T5	1952	1	0	0
T6	8448	0	0	0
T10	0	4	0	0
T11	0	14	0	0
T14	0	17	0	0
T15	0	1	0	0
T16	1981	0	0	0
T17	2184	0	0	0
T18	2590	0	0	0
T19	6873	0	0	0
T20	0	2	0	0
T21	7654	0	0	0
T108	0	1	0	0
T109	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	112941064	2370	0	0
TransStop_A	112941064	1228	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112941064	2370	0	0
T1	394492	48	0	0
T2	151519	0	0	0
T3	319097	25	0	0
T5	1952	2	0	0
T6	8448	0	0	0
T10	0	9	0	0
T11	0	23	0	0
T14	0	26	0	0
T15	0	3	0	0
T16	1981	0	0	0
T17	2184	0	0	0
T18	2590	0	0	0
T19	6873	1	0	0
T20	0	8	0	0
T21	7654	0	0	0
T108	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112941064	1228	0	0
T1	394492	28	0	0
T2	151519	0	0	0
T3	319097	16	0	0
T9	107443	0	0	0
T10	617023	5	0	0
T11	0	12	0	0
T14	0	14	0	0
T15	0	1	0	0
T16	1981	0	0	0
T17	2184	0	0	0
T18	2590	0	0	0
T19	6873	1	0	0
T20	5721	5	0	0
T109	0	5	0	0
T110	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	112941064	2345	0	0
TransStop_A	112941064	1209	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112941064	2345	0	0
T1	394492	46	0	0
T2	151519	0	0	0
T3	319097	27	0	0
T5	1952	3	0	0
T6	8448	0	0	0
T10	0	7	0	0
T11	0	22	0	0
T14	0	26	0	0
T15	0	3	0	0
T16	1981	0	0	0
T17	2184	0	0	0
T18	2590	0	0	0
T19	6873	0	0	0
T20	0	9	0	0
T21	7654	0	0	0
T108	0	2	0	0
T109	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112941064	1209	0	0
T1	394492	21	0	0
T2	151519	0	0	0
T3	319097	15	0	0
T5	1952	1	0	0
T6	8448	0	0	0
T10	0	3	0	0
T11	0	14	0	0
T14	0	11	0	0
T15	0	1	0	0
T16	1981	0	0	0
T17	2184	0	0	0
T18	2590	0	0	0
T19	6873	0	0	0
T20	0	5	0	0
T21	7654	0	0	0
T109	0	3	0	0
T110	0	4	0	0