Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	41079778	523918	0	0
clk_enables_rd_A	41079778	10193	0	0
clk_hints_rd_A	41079778	9123	0	0
extclk_ctrl_rd_A	41079778	13801	0	0
extclk_ctrl_regwen_rd_A	41079778	7764	0	0
jitter_enable_rd_A	41079778	19725	0	0
jitter_regwen_rd_A	41079778	7700	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41079778	523918	0	0
T1	394491	12118	0	0
T2	36363	0	0	0
T3	325096	16951	0	0
T9	25785	0	0	0
T10	317510	0	0	0
T11	0	13782	0	0
T15	0	15549	0	0
T16	1980	0	0	0
T17	1070	0	0	0
T18	1428	0	0	0
T19	756	0	0	0
T20	1944	0	0	0
T24	0	19952	0	0
T52	0	14112	0	0
T62	0	10828	0	0
T63	0	8635	0	0
T64	0	3518	0	0
T65	0	3424	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41079778	10193	0	0
T10	317510	3	0	0
T11	395965	0	0	0
T12	31177	0	0	0
T14	0	16	0	0
T20	1944	0	0	0
T22	43863	0	0	0
T25	43791	0	0	0
T26	143138	0	0	0
T27	913	0	0	0
T30	0	7	0	0
T62	0	408	0	0
T64	0	298	0	0
T65	0	62	0	0
T108	1875	0	0	0
T129	0	5	0	0
T130	0	186	0	0
T131	0	153	0	0
T132	0	739	0	0
T133	1791	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41079778	9123	0	0
T10	317510	16	0	0
T11	395965	0	0	0
T12	31177	0	0	0
T14	0	12	0	0
T20	1944	0	0	0
T22	43863	0	0	0
T25	43791	0	0	0
T26	143138	0	0	0
T27	913	0	0	0
T30	0	6	0	0
T62	0	384	0	0
T64	0	171	0	0
T65	0	100	0	0
T108	1875	0	0	0
T129	0	2	0	0
T130	0	198	0	0
T131	0	159	0	0
T132	0	709	0	0
T133	1791	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41079778	13801	0	0
T1	394491	0	0	0
T2	36363	0	0	0
T3	325096	0	0	0
T9	25785	0	0	0
T10	317510	23	0	0
T14	0	84	0	0
T16	1980	0	0	0
T17	1070	0	0	0
T18	1428	0	0	0
T19	756	0	0	0
T21	1836	38	0	0
T62	0	688	0	0
T106	0	41	0	0
T107	0	57	0	0
T134	0	4	0	0
T135	0	43	0	0
T136	0	20	0	0
T137	0	84	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41079778	7764	0	0
T29	170022	0	0	0
T39	0	18	0	0
T62	367656	442	0	0
T64	0	209	0	0
T65	0	83	0	0
T67	16814	0	0	0
T68	129313	0	0	0
T130	0	156	0	0
T131	0	143	0	0
T132	0	724	0	0
T137	2419	0	0	0
T138	0	48	0	0
T139	0	10	0	0
T140	0	27	0	0
T141	1329	0	0	0
T142	1133	0	0	0
T143	776	0	0	0
T144	1194	0	0	0
T145	2027	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41079778	19725	0	0
T10	317510	259	0	0
T11	395965	0	0	0
T12	31177	0	0	0
T14	0	571	0	0
T20	1944	0	0	0
T22	43863	0	0	0
T25	43791	0	0	0
T26	143138	0	0	0
T27	913	0	0	0
T30	0	206	0	0
T62	0	1042	0	0
T64	0	167	0	0
T65	0	72	0	0
T108	1875	0	0	0
T129	0	115	0	0
T130	0	638	0	0
T131	0	408	0	0
T133	1791	0	0	0
T146	0	103	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41079778	7700	0	0
T29	170022	0	0	0
T62	367656	446	0	0
T64	0	224	0	0
T65	0	64	0	0
T67	16814	0	0	0
T68	129313	0	0	0
T130	0	205	0	0
T131	0	174	0	0
T132	0	834	0	0
T137	2419	0	0	0
T141	1329	0	0	0
T142	1133	0	0	0
T143	776	0	0	0
T144	1194	0	0	0
T145	2027	0	0	0
T147	0	137	0	0
T148	0	403	0	0
T149	0	274	0	0
T150	0	74	0	0