Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	120458136	478	0	0
StatusRise_A	120458136	478	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120458136	478	0	0
T3	975288	0	0	0
T9	77355	0	0	0
T10	952530	0	0	0
T18	4284	14	0	0
T19	2268	0	0	0
T20	5832	0	0	0
T22	131589	0	0	0
T25	131373	0	0	0
T26	429414	0	0	0
T31	0	4	0	0
T32	0	8	0	0
T50	0	8	0	0
T133	5373	0	0	0
T144	0	8	0	0
T151	0	11	0	0
T152	0	8	0	0
T153	0	8	0	0
T154	0	7	0	0
T155	0	12	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120458136	478	0	0
T3	975288	0	0	0
T9	77355	0	0	0
T10	952530	0	0	0
T18	4284	14	0	0
T19	2268	0	0	0
T20	5832	0	0	0
T22	131589	0	0	0
T25	131373	0	0	0
T26	429414	0	0	0
T31	0	4	0	0
T32	0	8	0	0
T50	0	8	0	0
T133	5373	0	0	0
T144	0	8	0	0
T151	0	11	0	0
T152	0	8	0	0
T153	0	8	0	0
T154	0	7	0	0
T155	0	12	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	40152712	164	0	0
StatusRise_A	40152712	164	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	164	0	0
T3	325096	0	0	0
T9	25785	0	0	0
T10	317510	0	0	0
T18	1428	5	0	0
T19	756	0	0	0
T20	1944	0	0	0
T22	43863	0	0	0
T25	43791	0	0	0
T26	143138	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T50	0	2	0	0
T133	1791	0	0	0
T144	0	2	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	3	0	0
T154	0	3	0	0
T155	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	164	0	0
T3	325096	0	0	0
T9	25785	0	0	0
T10	317510	0	0	0
T18	1428	5	0	0
T19	756	0	0	0
T20	1944	0	0	0
T22	43863	0	0	0
T25	43791	0	0	0
T26	143138	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T50	0	2	0	0
T133	1791	0	0	0
T144	0	2	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	3	0	0
T154	0	3	0	0
T155	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	40152712	161	0	0
StatusRise_A	40152712	161	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	161	0	0
T3	325096	0	0	0
T9	25785	0	0	0
T10	317510	0	0	0
T18	1428	5	0	0
T19	756	0	0	0
T20	1944	0	0	0
T22	43863	0	0	0
T25	43791	0	0	0
T26	143138	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T50	0	3	0	0
T133	1791	0	0	0
T144	0	3	0	0
T151	0	3	0	0
T152	0	2	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	161	0	0
T3	325096	0	0	0
T9	25785	0	0	0
T10	317510	0	0	0
T18	1428	5	0	0
T19	756	0	0	0
T20	1944	0	0	0
T22	43863	0	0	0
T25	43791	0	0	0
T26	143138	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T50	0	3	0	0
T133	1791	0	0	0
T144	0	3	0	0
T151	0	3	0	0
T152	0	2	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	40152712	153	0	0
StatusRise_A	40152712	153	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	153	0	0
T3	325096	0	0	0
T9	25785	0	0	0
T10	317510	0	0	0
T18	1428	4	0	0
T19	756	0	0	0
T20	1944	0	0	0
T22	43863	0	0	0
T25	43791	0	0	0
T26	143138	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T50	0	3	0	0
T133	1791	0	0	0
T144	0	3	0	0
T151	0	2	0	0
T152	0	3	0	0
T153	0	2	0	0
T154	0	2	0	0
T155	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40152712	153	0	0
T3	325096	0	0	0
T9	25785	0	0	0
T10	317510	0	0	0
T18	1428	4	0	0
T19	756	0	0	0
T20	1944	0	0	0
T22	43863	0	0	0
T25	43791	0	0	0
T26	143138	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T50	0	3	0	0
T133	1791	0	0	0
T144	0	3	0	0
T151	0	2	0	0
T152	0	3	0	0
T153	0	2	0	0
T154	0	2	0	0
T155	0	4	0	0