Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	1194431088	33426	0	0
CgEnOn_A	1194431088	23937	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194431088	33426	0	0
T1	3197036	221	0	0
T2	1260300	6	0	0
T3	2734632	39	0	0
T4	7584	9	0	0
T5	11934	8	0	0
T6	52393	3	0	0
T9	498446	0	0	0
T10	2829999	13	0	0
T11	0	26	0	0
T16	16899	3	0	0
T17	18115	3	0	0
T18	28052	48	0	0
T19	74084	4	0	0
T20	26480	9	0	0
T21	47605	3	0	0
T22	447503	0	0	0
T25	439541	0	0	0
T26	335345	0	0	0
T31	0	11	0	0
T32	0	15	0	0
T62	0	5	0	0
T133	4441	0	0	0
T144	0	15	0	0
T151	0	15	0	0
T152	0	10	0	0
T153	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1194431088	23937	0	0
T1	3197036	191	0	0
T2	1260300	0	0	0
T3	2734632	128	0	0
T4	7584	6	0	0
T5	11934	5	0	0
T6	52393	0	0	0
T9	498446	0	0	0
T10	2829999	52	0	0
T11	0	196	0	0
T14	0	94	0	0
T16	16899	0	0	0
T17	18115	0	0	0
T18	28052	45	0	0
T19	74084	1	0	0
T20	26480	9	0	0
T21	47605	0	0	0
T22	447503	0	0	0
T25	439541	0	0	0
T26	335345	0	0	0
T31	0	17	0	0
T32	0	15	0	0
T62	0	4	0	0
T108	0	4	0	0
T133	4441	33	0	0
T144	0	15	0	0
T151	0	15	0	0
T152	0	10	0	0
T153	0	15	0	0
T154	0	2	0	0
T156	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	50565137	180	0	0
CgEnOn_A	50565137	180	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50565137	180	0	0
T1	176139	1	0	0
T2	72647	0	0	0
T3	144609	2	0	0
T9	51538	0	0	0
T10	287589	0	0	0
T16	1058	0	0	0
T17	1036	0	0	0
T18	1235	5	0	0
T19	3265	0	0	0
T20	2720	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T62	0	1	0	0
T144	0	3	0	0
T151	0	3	0	0
T152	0	2	0	0
T153	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50565137	180	0	0
T1	176139	1	0	0
T2	72647	0	0	0
T3	144609	2	0	0
T9	51538	0	0	0
T10	287589	0	0	0
T16	1058	0	0	0
T17	1036	0	0	0
T18	1235	5	0	0
T19	3265	0	0	0
T20	2720	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T62	0	1	0	0
T144	0	3	0	0
T151	0	3	0	0
T152	0	2	0	0
T153	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	25282098	180	0	0
CgEnOn_A	25282098	180	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25282098	180	0	0
T1	88065	1	0	0
T2	36323	0	0	0
T3	72303	2	0	0
T9	25769	0	0	0
T10	143795	0	0	0
T16	527	0	0	0
T17	518	0	0	0
T18	617	5	0	0
T19	1633	0	0	0
T20	1360	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T62	0	1	0	0
T144	0	3	0	0
T151	0	3	0	0
T152	0	2	0	0
T153	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25282098	180	0	0
T1	88065	1	0	0
T2	36323	0	0	0
T3	72303	2	0	0
T9	25769	0	0	0
T10	143795	0	0	0
T16	527	0	0	0
T17	518	0	0	0
T18	617	5	0	0
T19	1633	0	0	0
T20	1360	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T62	0	1	0	0
T144	0	3	0	0
T151	0	3	0	0
T152	0	2	0	0
T153	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	25282098	180	0	0
CgEnOn_A	25282098	180	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25282098	180	0	0
T1	88065	1	0	0
T2	36323	0	0	0
T3	72303	2	0	0
T9	25769	0	0	0
T10	143795	0	0	0
T16	527	0	0	0
T17	518	0	0	0
T18	617	5	0	0
T19	1633	0	0	0
T20	1360	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T62	0	1	0	0
T144	0	3	0	0
T151	0	3	0	0
T152	0	2	0	0
T153	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25282098	180	0	0
T1	88065	1	0	0
T2	36323	0	0	0
T3	72303	2	0	0
T9	25769	0	0	0
T10	143795	0	0	0
T16	527	0	0	0
T17	518	0	0	0
T18	617	5	0	0
T19	1633	0	0	0
T20	1360	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T62	0	1	0	0
T144	0	3	0	0
T151	0	3	0	0
T152	0	2	0	0
T153	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	25282098	180	0	0
CgEnOn_A	25282098	180	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25282098	180	0	0
T1	88065	1	0	0
T2	36323	0	0	0
T3	72303	2	0	0
T9	25769	0	0	0
T10	143795	0	0	0
T16	527	0	0	0
T17	518	0	0	0
T18	617	5	0	0
T19	1633	0	0	0
T20	1360	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T62	0	1	0	0
T144	0	3	0	0
T151	0	3	0	0
T152	0	2	0	0
T153	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25282098	180	0	0
T1	88065	1	0	0
T2	36323	0	0	0
T3	72303	2	0	0
T9	25769	0	0	0
T10	143795	0	0	0
T16	527	0	0	0
T17	518	0	0	0
T18	617	5	0	0
T19	1633	0	0	0
T20	1360	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T62	0	1	0	0
T144	0	3	0	0
T151	0	3	0	0
T152	0	2	0	0
T153	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103025813	180	0	0
CgEnOn_A	103025813	166	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103025813	180	0	0
T1	362588	1	0	0
T2	145454	0	0	0
T3	305369	2	0	0
T9	103142	0	0	0
T10	575045	0	0	0
T16	1902	0	0	0
T17	2096	0	0	0
T18	2549	5	0	0
T19	6597	0	0	0
T20	5492	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T62	0	1	0	0
T144	0	3	0	0
T151	0	3	0	0
T152	0	2	0	0
T153	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103025813	166	0	0
T1	362588	1	0	0
T2	145454	0	0	0
T3	305369	1	0	0
T9	103142	0	0	0
T10	575045	0	0	0
T16	1902	0	0	0
T17	2096	0	0	0
T18	2549	5	0	0
T19	6597	0	0	0
T20	5492	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T144	0	3	0	0
T151	0	3	0	0
T152	0	2	0	0
T153	0	3	0	0
T154	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	112940603	169	0	0
CgEnOn_A	112940603	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112940603	169	0	0
T3	319096	0	0	0
T9	107443	0	0	0
T10	617022	0	0	0
T18	2589	5	0	0
T19	6872	0	0	0
T20	5721	0	0	0
T22	182767	0	0	0
T25	178395	0	0	0
T26	134058	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T50	0	2	0	0
T133	1791	0	0	0
T144	0	2	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	3	0	0
T154	0	3	0	0
T155	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112940603	164	0	0
T3	319096	0	0	0
T9	107443	0	0	0
T10	617022	0	0	0
T18	2589	5	0	0
T19	6872	0	0	0
T20	5721	0	0	0
T22	182767	0	0	0
T25	178395	0	0	0
T26	134058	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T50	0	2	0	0
T133	1791	0	0	0
T144	0	2	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	3	0	0
T154	0	3	0	0
T155	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	112940603	169	0	0
CgEnOn_A	112940603	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112940603	169	0	0
T3	319096	0	0	0
T9	107443	0	0	0
T10	617022	0	0	0
T18	2589	5	0	0
T19	6872	0	0	0
T20	5721	0	0	0
T22	182767	0	0	0
T25	178395	0	0	0
T26	134058	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T50	0	2	0	0
T133	1791	0	0	0
T144	0	2	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	3	0	0
T154	0	3	0	0
T155	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112940603	164	0	0
T3	319096	0	0	0
T9	107443	0	0	0
T10	617022	0	0	0
T18	2589	5	0	0
T19	6872	0	0	0
T20	5721	0	0	0
T22	182767	0	0	0
T25	178395	0	0	0
T26	134058	0	0	0
T31	0	1	0	0
T32	0	3	0	0
T50	0	2	0	0
T133	1791	0	0	0
T144	0	2	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	3	0	0
T154	0	3	0	0
T155	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	54238589	161	0	0
CgEnOn_A	54238589	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54238589	161	0	0
T3	153169	0	0	0
T9	51573	0	0	0
T10	301936	0	0	0
T11	0	2	0	0
T18	1241	4	0	0
T19	3298	0	0	0
T20	2746	0	0	0
T22	81969	0	0	0
T25	82751	0	0	0
T26	67229	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T63	0	1	0	0
T133	859	0	0	0
T144	0	3	0	0
T151	0	2	0	0
T152	0	3	0	0
T153	0	2	0	0
T154	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54238589	157	0	0
T3	153169	0	0	0
T9	51573	0	0	0
T10	301936	0	0	0
T18	1241	4	0	0
T19	3298	0	0	0
T20	2746	0	0	0
T22	81969	0	0	0
T25	82751	0	0	0
T26	67229	0	0	0
T31	0	1	0	0
T32	0	2	0	0
T50	0	3	0	0
T63	0	1	0	0
T133	859	0	0	0
T144	0	3	0	0
T151	0	2	0	0
T152	0	3	0	0
T153	0	2	0	0
T154	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T31,T32
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	25282098	5433	0	0
CgEnOn_A	25282098	3080	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25282098	5433	0	0
T1	88065	57	0	0
T2	36323	2	0	0
T4	839	3	0	0
T5	438	1	0	0
T6	2147	1	0	0
T16	527	1	0	0
T17	518	1	0	0
T18	617	6	0	0
T19	1633	1	0	0
T21	1988	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25282098	3080	0	0
T1	88065	47	0	0
T2	36323	0	0	0
T3	0	30	0	0
T4	839	2	0	0
T5	438	0	0	0
T6	2147	0	0	0
T10	0	14	0	0
T11	0	57	0	0
T14	0	30	0	0
T16	527	0	0	0
T17	518	0	0	0
T18	617	5	0	0
T19	1633	0	0	0
T21	1988	0	0	0
T31	0	2	0	0
T133	0	11	0	0
T156	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T31,T32
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	50565137	5476	0	0
CgEnOn_A	50565137	3123	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50565137	5476	0	0
T1	176139	56	0	0
T2	72647	2	0	0
T4	1677	3	0	0
T5	877	1	0	0
T6	4294	1	0	0
T16	1058	1	0	0
T17	1036	1	0	0
T18	1235	6	0	0
T19	3265	1	0	0
T21	3979	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50565137	3123	0	0
T1	176139	46	0	0
T2	72647	0	0	0
T3	0	32	0	0
T4	1677	2	0	0
T5	877	0	0	0
T6	4294	0	0	0
T10	0	12	0	0
T11	0	58	0	0
T14	0	34	0	0
T16	1058	0	0	0
T17	1036	0	0	0
T18	1235	5	0	0
T19	3265	0	0	0
T21	3979	0	0	0
T31	0	2	0	0
T133	0	11	0	0
T156	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T31,T32
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	103025813	5497	0	0
CgEnOn_A	103025813	3130	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103025813	5497	0	0
T1	362588	57	0	0
T2	145454	2	0	0
T4	3379	3	0	0
T5	1874	1	0	0
T6	8109	1	0	0
T16	1902	1	0	0
T17	2096	1	0	0
T18	2549	6	0	0
T19	6597	1	0	0
T21	7348	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	103025813	3130	0	0
T1	362588	47	0	0
T2	145454	0	0	0
T3	0	28	0	0
T4	3379	2	0	0
T5	1874	0	0	0
T6	8109	0	0	0
T10	0	13	0	0
T11	0	55	0	0
T14	0	30	0	0
T16	1902	0	0	0
T17	2096	0	0	0
T18	2549	5	0	0
T19	6597	0	0	0
T21	7348	0	0	0
T31	0	2	0	0
T133	0	11	0	0
T156	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T18,T31,T32
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	54238589	5478	0	0
CgEnOn_A	54238589	3110	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54238589	5478	0	0
T1	189358	59	0	0
T2	72730	2	0	0
T4	1689	3	0	0
T5	937	1	0	0
T6	4055	1	0	0
T16	951	1	0	0
T17	1047	1	0	0
T18	1241	5	0	0
T19	3298	1	0	0
T21	3674	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54238589	3110	0	0
T1	189358	48	0	0
T2	72730	0	0	0
T3	0	27	0	0
T4	1689	2	0	0
T5	937	0	0	0
T6	4055	0	0	0
T10	0	14	0	0
T11	0	57	0	0
T14	0	28	0	0
T16	951	0	0	0
T17	1047	0	0	0
T18	1241	4	0	0
T19	3298	0	0	0
T21	3674	0	0	0
T31	0	1	0	0
T133	0	10	0	0
T156	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T5,T1,T19
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	112940603	2570	0	0
CgEnOn_A	112940603	2565	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112940603	2570	0	0
T1	394491	46	0	0
T2	151519	0	0	0
T3	319096	29	0	0
T5	1952	5	0	0
T6	8447	0	0	0
T10	0	13	0	0
T11	0	26	0	0
T16	1980	0	0	0
T17	2183	0	0	0
T18	2589	5	0	0
T19	6872	1	0	0
T20	0	9	0	0
T21	7654	0	0	0
T31	0	1	0	0
T108	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112940603	2565	0	0
T1	394491	46	0	0
T2	151519	0	0	0
T3	319096	29	0	0
T5	1952	5	0	0
T6	8447	0	0	0
T10	0	13	0	0
T11	0	26	0	0
T16	1980	0	0	0
T17	2183	0	0	0
T18	2589	5	0	0
T19	6872	1	0	0
T20	0	9	0	0
T21	7654	0	0	0
T31	0	1	0	0
T108	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T5,T1,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	112940603	2520	0	0
CgEnOn_A	112940603	2515	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112940603	2520	0	0
T1	394491	30	0	0
T2	151519	0	0	0
T3	319096	27	0	0
T5	1952	3	0	0
T6	8447	0	0	0
T10	0	9	0	0
T11	0	22	0	0
T14	0	29	0	0
T16	1980	0	0	0
T17	2183	0	0	0
T18	2589	5	0	0
T19	6872	0	0	0
T20	0	4	0	0
T21	7654	0	0	0
T31	0	1	0	0
T108	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112940603	2515	0	0
T1	394491	30	0	0
T2	151519	0	0	0
T3	319096	27	0	0
T5	1952	3	0	0
T6	8447	0	0	0
T10	0	9	0	0
T11	0	22	0	0
T14	0	29	0	0
T16	1980	0	0	0
T17	2183	0	0	0
T18	2589	5	0	0
T19	6872	0	0	0
T20	0	4	0	0
T21	7654	0	0	0
T31	0	1	0	0
T108	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T5,T1,T19
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	112940603	2539	0	0
CgEnOn_A	112940603	2534	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112940603	2539	0	0
T1	394491	48	0	0
T2	151519	0	0	0
T3	319096	25	0	0
T5	1952	2	0	0
T6	8447	0	0	0
T10	0	9	0	0
T11	0	23	0	0
T16	1980	0	0	0
T17	2183	0	0	0
T18	2589	5	0	0
T19	6872	1	0	0
T20	0	8	0	0
T21	7654	0	0	0
T31	0	1	0	0
T108	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112940603	2534	0	0
T1	394491	48	0	0
T2	151519	0	0	0
T3	319096	25	0	0
T5	1952	2	0	0
T6	8447	0	0	0
T10	0	9	0	0
T11	0	23	0	0
T16	1980	0	0	0
T17	2183	0	0	0
T18	2589	5	0	0
T19	6872	1	0	0
T20	0	8	0	0
T21	7654	0	0	0
T31	0	1	0	0
T108	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T18
1	0	Covered	T5,T1,T3
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	112940603	2514	0	0
CgEnOn_A	112940603	2509	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112940603	2514	0	0
T1	394491	46	0	0
T2	151519	0	0	0
T3	319096	27	0	0
T5	1952	3	0	0
T6	8447	0	0	0
T10	0	7	0	0
T11	0	22	0	0
T14	0	26	0	0
T16	1980	0	0	0
T17	2183	0	0	0
T18	2589	5	0	0
T19	6872	0	0	0
T20	0	9	0	0
T21	7654	0	0	0
T31	0	1	0	0
T108	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112940603	2509	0	0
T1	394491	46	0	0
T2	151519	0	0	0
T3	319096	27	0	0
T5	1952	3	0	0
T6	8447	0	0	0
T10	0	7	0	0
T11	0	22	0	0
T14	0	26	0	0
T16	1980	0	0	0
T17	2183	0	0	0
T18	2589	5	0	0
T19	6872	0	0	0
T20	0	9	0	0
T21	7654	0	0	0
T31	0	1	0	0
T108	0	2	0	0