Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	196977	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

471283

1

T4

12

T5

25

T6

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	195554	1			T4	9		T5	42		T32	16
values[0x0]	223356	1			T4	7		T5	25		T6	19
values[0x1]	249350	1			T4	12		T5	14		T6	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	136148	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

532112

1

T4

15

T5

34

T6

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2230	1			T12	9		T13	2		T135	2
valid_sources[0x01]	2101	1			T1	2		T134	5		T12	2
valid_sources[0x02]	2401	1			T1	1		T2	2		T12	3
valid_sources[0x03]	3105	1			T38	126		T133	2		T3	36
valid_sources[0x04]	2339	1			T36	1		T2	2		T114	2
valid_sources[0x05]	3092	1			T6	1		T2	2		T12	4
valid_sources[0x06]	2303	1			T36	1		T1	1		T26	1
valid_sources[0x07]	2626	1			T4	28		T36	1		T1	3
valid_sources[0x08]	1996	1			T113	1		T133	1		T134	1
valid_sources[0x09]	2472	1			T2	1		T26	4		T113	1
valid_sources[0x0a]	2414	1			T2	1		T177	1		T208	1
valid_sources[0x0b]	2140	1			T36	2		T2	2		T113	1
valid_sources[0x0c]	3163	1			T2	1		T12	3		T13	1
valid_sources[0x0d]	2160	1			T6	1		T2	1		T27	1
valid_sources[0x0e]	2598	1			T2	1		T133	7		T12	3
valid_sources[0x0f]	2613	1			T12	7		T13	6		T41	1
valid_sources[0x10]	2062	1			T6	1		T32	11		T2	1
valid_sources[0x11]	2791	1			T2	2		T12	5		T162	1
valid_sources[0x12]	5702	1			T1	1		T2	1		T28	8
valid_sources[0x13]	2373	1			T36	1		T1	1		T202	1
valid_sources[0x14]	2920	1			T1	1		T2	1		T27	1
valid_sources[0x15]	2593	1			T2	1		T26	1		T113	1
valid_sources[0x16]	3188	1			T113	1		T41	1		T104	4
valid_sources[0x17]	2945	1			T2	1		T12	8		T41	1
valid_sources[0x18]	2388	1			T36	3		T1	1		T114	1
valid_sources[0x19]	2260	1			T2	1		T22	2		T26	2
valid_sources[0x1a]	2519	1			T2	3		T26	2		T3	21
valid_sources[0x1b]	2200	1			T1	4		T13	4		T41	1
valid_sources[0x1c]	2668	1			T2	2		T26	1		T114	1
valid_sources[0x1d]	2451	1			T5	2		T28	3		T113	1
valid_sources[0x1e]	2080	1			T36	1		T2	4		T12	1
valid_sources[0x1f]	2677	1			T28	6		T113	1		T133	29
valid_sources[0x20]	2507	1			T2	3		T113	3		T12	4
valid_sources[0x21]	2811	1			T2	1		T25	1		T26	1
valid_sources[0x22]	2224	1			T5	5		T113	1		T12	1
valid_sources[0x23]	2306	1			T2	1		T114	1		T12	1
valid_sources[0x24]	3359	1			T2	1		T113	1		T12	4
valid_sources[0x25]	3872	1			T2	1		T26	2		T113	6
valid_sources[0x26]	2589	1			T2	2		T22	5		T113	2
valid_sources[0x27]	2820	1			T13	4		T41	1		T30	3
valid_sources[0x28]	2345	1			T5	1		T2	2		T113	2
valid_sources[0x29]	2646	1			T1	2		T2	3		T12	1
valid_sources[0x2a]	5754	1			T1	1		T22	6		T202	1
valid_sources[0x2b]	2273	1			T5	2		T2	1		T113	5
valid_sources[0x2c]	2833	1			T22	2		T113	2		T12	5
valid_sources[0x2d]	3088	1			T36	1		T2	1		T12	1
valid_sources[0x2e]	2128	1			T6	7		T1	2		T2	1
valid_sources[0x2f]	2016	1			T32	4		T36	1		T2	1
valid_sources[0x30]	2274	1			T1	4		T12	1		T131	2
valid_sources[0x31]	3100	1			T36	1		T1	1		T113	1
valid_sources[0x32]	2757	1			T28	1		T113	1		T114	2
valid_sources[0x33]	2857	1			T1	2		T29	49		T12	7
valid_sources[0x34]	2434	1			T22	5		T26	4		T12	2
valid_sources[0x35]	3334	1			T2	2		T12	1		T13	1
valid_sources[0x36]	2278	1			T113	1		T12	3		T13	15
valid_sources[0x37]	3202	1			T36	1		T2	1		T113	2
valid_sources[0x38]	2906	1			T36	1		T37	33		T28	8
valid_sources[0x39]	2533	1			T25	1		T113	1		T114	1
valid_sources[0x3a]	2553	1			T1	3		T2	1		T27	1
valid_sources[0x3b]	2554	1			T2	1		T133	6		T134	9
valid_sources[0x3c]	4765	1			T5	7		T28	9		T113	1
valid_sources[0x3d]	2331	1			T6	1		T62	2		T12	1
valid_sources[0x3e]	2211	1			T103	5		T12	2		T13	7
valid_sources[0x3f]	2711	1			T2	4		T113	1		T12	4
valid_sources[0x40]	2212	1			T36	1		T25	1		T12	2
valid_sources[0x41]	2569	1			T2	3		T114	1		T12	2
valid_sources[0x42]	2692	1			T2	2		T113	3		T12	3
valid_sources[0x43]	2595	1			T2	1		T22	2		T133	3
valid_sources[0x44]	2150	1			T36	1		T113	1		T133	1
valid_sources[0x45]	2485	1			T134	3		T12	5		T131	1
valid_sources[0x46]	2392	1			T1	1		T2	3		T113	1
valid_sources[0x47]	2378	1			T26	1		T113	2		T12	6
valid_sources[0x48]	2903	1			T114	3		T12	5		T13	8
valid_sources[0x49]	2187	1			T1	1		T2	2		T12	1
valid_sources[0x4a]	2013	1			T2	1		T113	2		T114	1
valid_sources[0x4b]	2544	1			T5	1		T36	1		T2	2
valid_sources[0x4c]	2259	1			T2	1		T12	3		T13	1
valid_sources[0x4d]	2294	1			T2	3		T113	1		T114	1
valid_sources[0x4e]	2371	1			T6	1		T113	1		T41	3
valid_sources[0x4f]	2665	1			T34	3		T2	1		T26	1
valid_sources[0x50]	2371	1			T2	3		T114	1		T134	1
valid_sources[0x51]	2611	1			T12	4		T41	1		T104	1
valid_sources[0x52]	1915	1			T6	4		T2	3		T28	3
valid_sources[0x53]	2674	1			T1	4		T2	2		T28	2
valid_sources[0x54]	2685	1			T2	2		T26	2		T133	9
valid_sources[0x55]	2134	1			T2	2		T12	2		T135	1
valid_sources[0x56]	2425	1			T34	5		T12	5		T209	2
valid_sources[0x57]	2611	1			T113	2		T114	2		T12	1
valid_sources[0x58]	2583	1			T32	1		T37	9		T25	1
valid_sources[0x59]	2936	1			T2	1		T13	1		T60	1
valid_sources[0x5a]	2750	1			T2	2		T113	3		T12	5
valid_sources[0x5b]	3866	1			T2	2		T113	2		T62	1
valid_sources[0x5c]	2348	1			T2	3		T12	3		T13	1
valid_sources[0x5d]	2667	1			T2	1		T13	1		T135	1
valid_sources[0x5e]	2259	1			T36	1		T2	3		T25	1
valid_sources[0x5f]	2490	1			T2	1		T208	1		T30	9
valid_sources[0x60]	3067	1			T5	3		T2	4		T113	1
valid_sources[0x61]	2588	1			T12	4		T30	4		T31	2
valid_sources[0x62]	2736	1			T36	1		T1	1		T2	1
valid_sources[0x63]	2222	1			T2	1		T113	2		T114	1
valid_sources[0x64]	3257	1			T5	8		T2	1		T114	2
valid_sources[0x65]	2591	1			T2	2		T12	3		T158	2
valid_sources[0x66]	2156	1			T113	1		T12	4		T13	2
valid_sources[0x67]	2144	1			T36	1		T12	1		T13	2
valid_sources[0x68]	2137	1			T37	7		T1	1		T2	1
valid_sources[0x69]	2706	1			T2	1		T26	1		T41	2
valid_sources[0x6a]	2772	1			T6	3		T36	1		T2	2
valid_sources[0x6b]	2144	1			T2	1		T113	1		T114	1
valid_sources[0x6c]	2757	1			T36	1		T2	2		T26	2
valid_sources[0x6d]	2143	1			T5	6		T26	1		T114	1
valid_sources[0x6e]	2553	1			T12	5		T13	1		T204	1
valid_sources[0x6f]	2135	1			T22	1		T12	4		T41	1
valid_sources[0x70]	2301	1			T6	1		T12	1		T210	3
valid_sources[0x71]	2434	1			T36	1		T2	1		T26	3
valid_sources[0x72]	2149	1			T113	1		T114	1		T134	6
valid_sources[0x73]	2756	1			T2	1		T113	1		T12	2
valid_sources[0x74]	2788	1			T2	1		T113	1		T203	1
valid_sources[0x75]	2781	1			T34	2		T2	2		T25	1
valid_sources[0x76]	2118	1			T5	6		T2	1		T12	2
valid_sources[0x77]	2516	1			T2	1		T25	1		T12	6
valid_sources[0x78]	2120	1			T26	1		T113	1		T12	4
valid_sources[0x79]	2519	1			T36	1		T25	1		T113	1
valid_sources[0x7a]	2817	1			T2	2		T25	1		T26	1
valid_sources[0x7b]	2474	1			T6	1		T36	1		T2	2
valid_sources[0x7c]	3645	1			T5	5		T1	2		T2	2
valid_sources[0x7d]	2370	1			T113	2		T135	1		T30	2
valid_sources[0x7e]	2394	1			T36	1		T2	2		T12	1
valid_sources[0x7f]	2249	1			T1	1		T2	1		T133	3
valid_sources[0x80]	2243	1			T2	1		T113	1		T133	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

132181

1

T4

6

T5

17

T32

9

values[0x0]

all_enables

biggest_size

181009

1

T4

3

T5

6

T6

1

values[0x1]

all_enables

biggest_size

158093

1

T4

3

T5

2

T6

3