Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T33
0	1	Covered	T6,T202,T203
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T53
1	0	Covered	T33,T23,T59
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	153575505	8396	0	0
GateOpen_A	153575505	14563	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153575505	8396	0	0
T1	94181	0	0	0
T5	9319	4	0	0
T6	3577	37	0	0
T21	0	4	0	0
T23	0	26	0	0
T26	0	4	0	0
T28	0	4	0	0
T32	11562	0	0	0
T33	2993	4	0	0
T34	4628	0	0	0
T35	14232	0	0	0
T36	13969	0	0	0
T37	81168	0	0	0
T38	124577	0	0	0
T59	0	7	0	0
T202	0	5	0	0
T203	0	13	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153575505	14563	0	0
T4	3448	4	0	0
T5	9319	8	0	0
T6	3577	41	0	0
T21	0	4	0	0
T22	0	4	0	0
T32	11562	4	0	0
T33	2993	8	0	0
T34	4628	0	0	0
T35	14232	0	0	0
T36	13969	4	0	0
T37	81168	0	0	0
T38	124577	0	0	0
T53	0	200	0	0
T54	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T33
0	1	Covered	T6,T202,T203
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T53
1	0	Covered	T33,T23,T59
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	16507240	1990	0	0
GateOpen_A	16507240	3527	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16507240	1990	0	0
T1	10454	0	0	0
T5	1032	1	0	0
T6	375	8	0	0
T21	0	1	0	0
T23	0	7	0	0
T26	0	1	0	0
T28	0	1	0	0
T32	1281	0	0	0
T33	313	1	0	0
T34	511	0	0	0
T35	1649	0	0	0
T36	1669	0	0	0
T37	9417	0	0	0
T38	13824	0	0	0
T59	0	1	0	0
T202	0	1	0	0
T203	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16507240	3527	0	0
T4	410	1	0	0
T5	1032	2	0	0
T6	375	9	0	0
T21	0	1	0	0
T22	0	1	0	0
T32	1281	1	0	0
T33	313	2	0	0
T34	511	0	0	0
T35	1649	0	0	0
T36	1669	1	0	0
T37	9417	0	0	0
T38	13824	0	0	0
T53	0	50	0	0
T54	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T33
0	1	Covered	T6,T202,T203
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T53
1	0	Covered	T33,T23,T59
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	33014861	2137	0	0
GateOpen_A	33014861	3674	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33014861	2137	0	0
T1	20907	0	0	0
T5	2063	1	0	0
T6	750	11	0	0
T21	0	1	0	0
T23	0	7	0	0
T26	0	1	0	0
T28	0	1	0	0
T32	2561	0	0	0
T33	626	1	0	0
T34	1024	0	0	0
T35	3301	0	0	0
T36	3340	0	0	0
T37	18835	0	0	0
T38	27648	0	0	0
T59	0	1	0	0
T202	0	1	0	0
T203	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33014861	3674	0	0
T4	820	1	0	0
T5	2063	2	0	0
T6	750	12	0	0
T21	0	1	0	0
T22	0	1	0	0
T32	2561	1	0	0
T33	626	2	0	0
T34	1024	0	0	0
T35	3301	0	0	0
T36	3340	1	0	0
T37	18835	0	0	0
T38	27648	0	0	0
T53	0	50	0	0
T54	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T33
0	1	Covered	T6,T202,T203
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T53
1	0	Covered	T33,T23,T59
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	67850759	2140	0	0
GateOpen_A	67850759	3687	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67850759	2140	0	0
T1	41880	0	0	0
T5	4149	1	0	0
T6	1635	9	0	0
T21	0	1	0	0
T23	0	7	0	0
T26	0	1	0	0
T28	0	1	0	0
T32	5147	0	0	0
T33	1372	1	0	0
T34	2062	0	0	0
T35	6188	0	0	0
T36	5973	0	0	0
T37	35277	0	0	0
T38	55403	0	0	0
T59	0	1	0	0
T202	0	1	0	0
T203	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67850759	3687	0	0
T4	1479	1	0	0
T5	4149	2	0	0
T6	1635	10	0	0
T21	0	1	0	0
T22	0	1	0	0
T32	5147	1	0	0
T33	1372	2	0	0
T34	2062	0	0	0
T35	6188	0	0	0
T36	5973	1	0	0
T37	35277	0	0	0
T38	55403	0	0	0
T53	0	50	0	0
T54	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T33
0	1	Covered	T6,T202,T203
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T53
1	0	Covered	T33,T23,T59
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	36202645	2129	0	0
GateOpen_A	36202645	3675	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36202645	2129	0	0
T1	20940	0	0	0
T5	2075	1	0	0
T6	817	9	0	0
T21	0	1	0	0
T23	0	5	0	0
T26	0	1	0	0
T28	0	1	0	0
T32	2573	0	0	0
T33	682	1	0	0
T34	1031	0	0	0
T35	3094	0	0	0
T36	2987	0	0	0
T37	17639	0	0	0
T38	27702	0	0	0
T59	0	4	0	0
T202	0	2	0	0
T203	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36202645	3675	0	0
T4	739	1	0	0
T5	2075	2	0	0
T6	817	10	0	0
T21	0	1	0	0
T22	0	1	0	0
T32	2573	1	0	0
T33	682	2	0	0
T34	1031	0	0	0
T35	3094	0	0	0
T36	2987	1	0	0
T37	17639	0	0	0
T38	27702	0	0	0
T53	0	50	0	0
T54	0	1	0	0