Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	195313995	32821	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195313995	32821	0	0
T2	621085	100	0	0
T10	0	149	0	0
T11	0	92	0	0
T14	0	46	0	0
T15	0	144	0	0
T16	0	99	0	0
T17	0	373	0	0
T18	0	140	0	0
T19	0	418	0	0
T20	0	340	0	0
T21	6530	0	0	0
T22	8795	0	0	0
T23	9370	0	0	0
T24	7565	0	0	0
T25	9145	0	0	0
T26	5440	0	0	0
T27	3400	0	0	0
T28	5720	0	0	0
T29	10025	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39062799	4751	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	4751	0	0
T2	124217	14	0	0
T10	0	24	0	0
T11	0	12	0	0
T14	0	8	0	0
T15	0	21	0	0
T16	0	16	0	0
T17	0	48	0	0
T18	0	20	0	0
T19	0	61	0	0
T20	0	45	0	0
T21	1306	0	0	0
T22	1759	0	0	0
T23	1874	0	0	0
T24	1513	0	0	0
T25	1829	0	0	0
T26	1088	0	0	0
T27	680	0	0	0
T28	1144	0	0	0
T29	2005	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39062799	4653	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	4653	0	0
T2	124217	13	0	0
T10	0	24	0	0
T11	0	12	0	0
T14	0	7	0	0
T15	0	21	0	0
T16	0	16	0	0
T17	0	47	0	0
T18	0	20	0	0
T19	0	52	0	0
T20	0	44	0	0
T21	1306	0	0	0
T22	1759	0	0	0
T23	1874	0	0	0
T24	1513	0	0	0
T25	1829	0	0	0
T26	1088	0	0	0
T27	680	0	0	0
T28	1144	0	0	0
T29	2005	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39062799	6559	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	6559	0	0
T2	124217	20	0	0
T10	0	30	0	0
T11	0	19	0	0
T14	0	10	0	0
T15	0	30	0	0
T16	0	20	0	0
T17	0	75	0	0
T18	0	28	0	0
T19	0	83	0	0
T20	0	68	0	0
T21	1306	0	0	0
T22	1759	0	0	0
T23	1874	0	0	0
T24	1513	0	0	0
T25	1829	0	0	0
T26	1088	0	0	0
T27	680	0	0	0
T28	1144	0	0	0
T29	2005	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39062799	6575	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	6575	0	0
T2	124217	20	0	0
T10	0	30	0	0
T11	0	18	0	0
T14	0	9	0	0
T15	0	28	0	0
T16	0	20	0	0
T17	0	77	0	0
T18	0	28	0	0
T19	0	85	0	0
T20	0	67	0	0
T21	1306	0	0	0
T22	1759	0	0	0
T23	1874	0	0	0
T24	1513	0	0	0
T25	1829	0	0	0
T26	1088	0	0	0
T27	680	0	0	0
T28	1144	0	0	0
T29	2005	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	39062799	10283	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	10283	0	0
T2	124217	33	0	0
T10	0	41	0	0
T11	0	31	0	0
T14	0	12	0	0
T15	0	44	0	0
T16	0	27	0	0
T17	0	126	0	0
T18	0	44	0	0
T19	0	137	0	0
T20	0	116	0	0
T21	1306	0	0	0
T22	1759	0	0	0
T23	1874	0	0	0
T24	1513	0	0	0
T25	1829	0	0	0
T26	1088	0	0	0
T27	680	0	0	0
T28	1144	0	0	0
T29	2005	0	0	0