Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

22                      
23         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T53,T12,T13

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	39062799	36261172	0	0
AllClkBypReqTrue_A	39062799	77832	0	0
IoClkBypReqFalse_A	39062799	36210057	0	2415
IoClkBypReqTrue_A	39062799	124463	0	0
LcClkBypAckFalse_A	39062799	36268158	0	0
LcClkBypAckTrue_A	39062799	70846	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	36261172	0	0
T4	1478	1267	0	0
T5	1036	999	0	0
T6	1634	1471	0	0
T32	1339	1297	0	0
T33	1460	1290	0	0
T34	2147	1934	0	0
T35	1610	1335	0	0
T36	1555	1376	0	0
T37	1836	1587	0	0
T38	2885	2876	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	77832	0	0
T4	1478	130	0	0
T5	1036	0	0	0
T6	1634	0	0	0
T22	0	149	0	0
T25	0	90	0	0
T32	1339	0	0	0
T33	1460	0	0	0
T34	2147	0	0	0
T35	1610	215	0	0
T36	1555	121	0	0
T37	1836	245	0	0
T38	2885	0	0	0
T103	0	328	0	0
T104	0	134	0	0
T130	0	492	0	0
T131	0	101	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	36210057	0	2415
T4	1478	1273	0	3
T5	1036	997	0	3
T6	1634	1469	0	3
T32	1339	1295	0	3
T33	1460	1288	0	3
T34	2147	1644	0	3
T35	1610	1315	0	3
T36	1555	1193	0	3
T37	1836	1780	0	3
T38	2885	2874	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	124463	0	0
T4	1478	122	0	0
T5	1036	0	0	0
T6	1634	0	0	0
T22	0	362	0	0
T24	0	26	0	0
T27	0	42	0	0
T32	1339	0	0	0
T33	1460	0	0	0
T34	2147	288	0	0
T35	1610	233	0	0
T36	1555	302	0	0
T37	1836	50	0	0
T38	2885	0	0	0
T103	0	523	0	0
T130	0	673	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	36268158	0	0
T4	1478	1288	0	0
T5	1036	999	0	0
T6	1634	1471	0	0
T32	1339	1297	0	0
T33	1460	1290	0	0
T34	2147	1844	0	0
T35	1610	1435	0	0
T36	1555	1377	0	0
T37	1836	1832	0	0
T38	2885	2876	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	70846	0	0
T4	1478	109	0	0
T5	1036	0	0	0
T6	1634	0	0	0
T22	0	105	0	0
T24	0	21	0	0
T27	0	38	0	0
T32	1339	0	0	0
T33	1460	0	0	0
T34	2147	90	0	0
T35	1610	115	0	0
T36	1555	120	0	0
T37	1836	0	0	0
T38	2885	0	0	0
T103	0	273	0	0
T130	0	358	0	0
T132	0	24	0	0