Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	302827480	8901	0	0
TransStop_A	302827480	4747	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302827480	8901	0	0
T1	198504	0	0	0
T5	17288	4	0	0
T6	6812	0	0	0
T26	0	4	0	0
T28	0	4	0	0
T29	0	16	0	0
T32	21444	11	0	0
T33	5752	0	0	0
T34	8592	0	0	0
T35	25780	0	0	0
T36	24888	0	0	0
T37	146992	0	0	0
T38	230852	36	0	0
T113	0	41	0	0
T114	0	22	0	0
T133	0	43	0	0
T134	0	30	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	302827480	4747	0	0
T1	198504	0	0	0
T5	17288	4	0	0
T6	6812	0	0	0
T26	0	4	0	0
T28	0	4	0	0
T29	0	3	0	0
T32	21444	0	0	0
T33	5752	0	0	0
T34	8592	0	0	0
T35	25780	0	0	0
T36	24888	0	0	0
T37	146992	0	0	0
T38	230852	22	0	0
T113	0	13	0	0
T114	0	9	0	0
T133	0	27	0	0
T134	0	11	0	0
T135	0	5	0	0
T136	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	75706870	2278	0	0
TransStop_A	75706870	1217	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706870	2278	0	0
T1	49626	0	0	0
T5	4322	1	0	0
T6	1703	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	4	0	0
T32	5361	3	0	0
T33	1438	0	0	0
T34	2148	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36748	0	0	0
T38	57713	7	0	0
T113	0	10	0	0
T114	0	8	0	0
T133	0	9	0	0
T134	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706870	1217	0	0
T1	49626	0	0	0
T5	4322	1	0	0
T6	1703	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	5361	0	0	0
T33	1438	0	0	0
T34	2148	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36748	0	0	0
T38	57713	4	0	0
T113	0	5	0	0
T114	0	3	0	0
T133	0	5	0	0
T134	0	3	0	0
T135	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	75706870	2229	0	0
TransStop_A	75706870	1190	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706870	2229	0	0
T1	49626	0	0	0
T5	4322	1	0	0
T6	1703	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	4	0	0
T32	5361	3	0	0
T33	1438	0	0	0
T34	2148	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36748	0	0	0
T38	57713	7	0	0
T113	0	7	0	0
T114	0	4	0	0
T133	0	9	0	0
T134	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706870	1190	0	0
T1	49626	0	0	0
T5	4322	1	0	0
T6	1703	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	2	0	0
T32	5361	0	0	0
T33	1438	0	0	0
T34	2148	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36748	0	0	0
T38	57713	4	0	0
T113	0	3	0	0
T114	0	1	0	0
T133	0	5	0	0
T134	0	3	0	0
T135	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	75706870	2217	0	0
TransStop_A	75706870	1170	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706870	2217	0	0
T1	49626	0	0	0
T5	4322	1	0	0
T6	1703	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	5	0	0
T32	5361	3	0	0
T33	1438	0	0	0
T34	2148	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36748	0	0	0
T38	57713	9	0	0
T113	0	11	0	0
T114	0	6	0	0
T133	0	12	0	0
T134	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706870	1170	0	0
T1	49626	0	0	0
T5	4322	1	0	0
T6	1703	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T32	5361	0	0	0
T33	1438	0	0	0
T34	2148	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36748	0	0	0
T38	57713	7	0	0
T113	0	3	0	0
T114	0	3	0	0
T133	0	9	0	0
T134	0	4	0	0
T135	0	1	0	0
T136	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	75706870	2177	0	0
TransStop_A	75706870	1170	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706870	2177	0	0
T1	49626	0	0	0
T5	4322	1	0	0
T6	1703	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	3	0	0
T32	5361	2	0	0
T33	1438	0	0	0
T34	2148	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36748	0	0	0
T38	57713	13	0	0
T113	0	13	0	0
T114	0	4	0	0
T133	0	13	0	0
T134	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706870	1170	0	0
T1	49626	0	0	0
T5	4322	1	0	0
T6	1703	0	0	0
T26	0	1	0	0
T28	0	1	0	0
T32	5361	0	0	0
T33	1438	0	0	0
T34	2148	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36748	0	0	0
T38	57713	7	0	0
T113	0	2	0	0
T114	0	2	0	0
T133	0	8	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	1	0	0