Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_div2.u_step_down_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T34,T35

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T34,T35
1	1	Covered	T4,T34,T35

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T34,T35
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	82380541	82378126	0	0
selKnown1	203550939	203548524	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	82380541	82378126	0	0
T4	1950	1947	0	0
T5	5155	5152	0	0
T6	1875	1872	0	0
T32	6402	6399	0	0
T33	1565	1562	0	0
T34	2511	2508	0	0
T35	7982	7979	0	0
T36	7934	7931	0	0
T37	45870	45867	0	0
T38	69120	69117	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	203550939	203548524	0	0
T4	4434	4431	0	0
T5	12447	12444	0	0
T6	4902	4899	0	0
T32	15438	15435	0	0
T33	4116	4113	0	0
T34	6186	6183	0	0
T35	18561	18558	0	0
T36	17919	17916	0	0
T37	105828	105825	0	0
T38	166209	166206	0	0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	33014455	33013650	0	0
selKnown1	67850313	67849508	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	33014455	33013650	0	0
T4	820	819	0	0
T5	2062	2061	0	0
T6	750	749	0	0
T32	2561	2560	0	0
T33	626	625	0	0
T34	1023	1022	0	0
T35	3300	3299	0	0
T36	3339	3338	0	0
T37	18835	18834	0	0
T38	27648	27647	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	67850313	67849508	0	0
T4	1478	1477	0	0
T5	4149	4148	0	0
T6	1634	1633	0	0
T32	5146	5145	0	0
T33	1372	1371	0	0
T34	2062	2061	0	0
T35	6187	6186	0	0
T36	5973	5972	0	0
T37	35276	35275	0	0
T38	55403	55402	0	0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T34,T35

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T34,T35
1	1	Covered	T4,T34,T35

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T34,T35
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	32859247	32858442	0	0
selKnown1	67850313	67849508	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	32859247	32858442	0	0
T4	720	719	0	0
T5	2062	2061	0	0
T6	750	749	0	0
T32	2561	2560	0	0
T33	626	625	0	0
T34	977	976	0	0
T35	3033	3032	0	0
T36	2926	2925	0	0
T37	17619	17618	0	0
T38	27648	27647	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	67850313	67849508	0	0
T4	1478	1477	0	0
T5	4149	4148	0	0
T6	1634	1633	0	0
T32	5146	5145	0	0
T33	1372	1371	0	0
T34	2062	2061	0	0
T35	6187	6186	0	0
T36	5973	5972	0	0
T37	35276	35275	0	0
T38	55403	55402	0	0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Unreachable

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Unreachable
1	1	Unreachable

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	16506839	16506034	0	0
selKnown1	67850313	67849508	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	16506839	16506034	0	0
T4	410	409	0	0
T5	1031	1030	0	0
T6	375	374	0	0
T32	1280	1279	0	0
T33	313	312	0	0
T34	511	510	0	0
T35	1649	1648	0	0
T36	1669	1668	0	0
T37	9416	9415	0	0
T38	13824	13823	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	67850313	67849508	0	0
T4	1478	1477	0	0
T5	4149	4148	0	0
T6	1634	1633	0	0
T32	5146	5145	0	0
T33	1372	1371	0	0
T34	2062	2061	0	0
T35	6187	6186	0	0
T36	5973	5972	0	0
T37	35276	35275	0	0
T38	55403	55402	0	0