Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	40020067	507275	0	0
clk_enables_rd_A	40020067	8636	0	0
clk_hints_rd_A	40020067	7791	0	0
extclk_ctrl_rd_A	40020067	10861	0	0
extclk_ctrl_regwen_rd_A	40020067	6880	0	0
jitter_enable_rd_A	40020067	14501	0	0
jitter_regwen_rd_A	40020067	7270	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40020067	507275	0	0
T18	47096	1113	0	0
T40	11388	0	0	0
T68	0	3186	0	0
T69	0	6376	0	0
T81	0	8572	0	0
T82	0	1658	0	0
T83	0	7569	0	0
T84	0	5426	0	0
T85	0	14647	0	0
T86	0	22361	0	0
T87	0	4039	0	0
T88	1997	0	0	0
T89	1233	0	0	0
T90	1629	0	0	0
T91	1835	0	0	0
T92	1852	0	0	0
T93	1690	0	0	0
T94	1083	0	0	0
T95	23799	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40020067	8636	0	0
T43	0	4	0	0
T61	7402	0	0	0
T68	0	77	0	0
T69	0	315	0	0
T81	0	309	0	0
T83	0	179	0	0
T136	1723	1	0	0
T154	0	3	0	0
T155	0	2	0	0
T156	0	1	0	0
T157	0	4	0	0
T158	2289	0	0	0
T159	1802	0	0	0
T160	953	0	0	0
T161	1111	0	0	0
T162	994	0	0	0
T163	2083	0	0	0
T164	1747	0	0	0
T165	2585	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40020067	7791	0	0
T10	34140	0	0	0
T55	13948	0	0	0
T68	0	84	0	0
T69	0	280	0	0
T81	0	315	0	0
T83	0	109	0	0
T154	2371	1	0	0
T155	0	2	0	0
T157	0	2	0	0
T166	0	3	0	0
T167	0	5	0	0
T168	0	432	0	0
T169	1647	0	0	0
T170	1756	0	0	0
T171	1528	0	0	0
T172	2720	0	0	0
T173	1370	0	0	0
T174	32716	0	0	0
T175	1528	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40020067	10861	0	0
T1	47639	0	0	0
T2	124217	0	0	0
T21	1306	0	0	0
T25	0	16	0	0
T34	2147	16	0	0
T35	1610	0	0	0
T36	1555	0	0	0
T37	1836	63	0	0
T38	2885	0	0	0
T53	13076	0	0	0
T54	1915	0	0	0
T105	0	3	0	0
T130	0	55	0	0
T158	0	48	0	0
T174	0	42	0	0
T176	0	2	0	0
T177	0	15	0	0
T178	0	43	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40020067	6880	0	0
T49	0	18	0	0
T68	0	77	0	0
T69	0	300	0	0
T81	0	328	0	0
T83	0	167	0	0
T105	1060	0	0	0
T128	0	21	0	0
T174	32716	16	0	0
T175	1528	0	0	0
T179	0	35	0	0
T180	0	27	0	0
T181	0	49	0	0
T182	1967	0	0	0
T183	1885	0	0	0
T184	2210	0	0	0
T185	1793	0	0	0
T186	965	0	0	0
T187	1389	0	0	0
T188	2680	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40020067	14501	0	0
T43	0	131	0	0
T61	7402	0	0	0
T68	0	497	0	0
T69	0	513	0	0
T81	0	533	0	0
T136	1723	57	0	0
T154	0	104	0	0
T155	0	126	0	0
T156	0	86	0	0
T157	0	92	0	0
T158	2289	0	0	0
T159	1802	0	0	0
T160	953	0	0	0
T161	1111	0	0	0
T162	994	0	0	0
T163	2083	0	0	0
T164	1747	0	0	0
T165	2585	0	0	0
T166	0	99	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40020067	7270	0	0
T45	48445	0	0	0
T68	97960	57	0	0
T69	254851	340	0	0
T81	298029	394	0	0
T82	68812	0	0	0
T83	223356	182	0	0
T168	0	396	0	0
T189	0	329	0	0
T190	0	193	0	0
T191	0	202	0	0
T192	0	225	0	0
T193	0	360	0	0
T194	2654	0	0	0
T195	1667	0	0	0
T196	1902	0	0	0
T197	1050	0	0	0