Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	117188397	406	0	0
StatusRise_A	117188397	406	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117188397	406	0	0
T1	142917	0	0	0
T2	372651	0	0	0
T23	0	18	0	0
T33	4380	4	0	0
T34	6441	0	0	0
T35	4830	0	0	0
T36	4665	0	0	0
T37	5508	0	0	0
T38	8655	0	0	0
T53	39228	0	0	0
T54	5745	0	0	0
T59	0	6	0	0
T164	0	11	0	0
T173	0	6	0	0
T186	0	8	0	0
T198	0	5	0	0
T199	0	10	0	0
T200	0	8	0	0
T201	0	18	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117188397	406	0	0
T1	142917	0	0	0
T2	372651	0	0	0
T23	0	18	0	0
T33	4380	4	0	0
T34	6441	0	0	0
T35	4830	0	0	0
T36	4665	0	0	0
T37	5508	0	0	0
T38	8655	0	0	0
T53	39228	0	0	0
T54	5745	0	0	0
T59	0	6	0	0
T164	0	11	0	0
T173	0	6	0	0
T186	0	8	0	0
T198	0	5	0	0
T199	0	10	0	0
T200	0	8	0	0
T201	0	18	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	39062799	133	0	0
StatusRise_A	39062799	133	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	133	0	0
T1	47639	0	0	0
T2	124217	0	0	0
T23	0	6	0	0
T33	1460	2	0	0
T34	2147	0	0	0
T35	1610	0	0	0
T36	1555	0	0	0
T37	1836	0	0	0
T38	2885	0	0	0
T53	13076	0	0	0
T54	1915	0	0	0
T59	0	1	0	0
T164	0	4	0	0
T173	0	3	0	0
T186	0	3	0	0
T198	0	2	0	0
T199	0	4	0	0
T200	0	3	0	0
T201	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	133	0	0
T1	47639	0	0	0
T2	124217	0	0	0
T23	0	6	0	0
T33	1460	2	0	0
T34	2147	0	0	0
T35	1610	0	0	0
T36	1555	0	0	0
T37	1836	0	0	0
T38	2885	0	0	0
T53	13076	0	0	0
T54	1915	0	0	0
T59	0	1	0	0
T164	0	4	0	0
T173	0	3	0	0
T186	0	3	0	0
T198	0	2	0	0
T199	0	4	0	0
T200	0	3	0	0
T201	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	39062799	133	0	0
StatusRise_A	39062799	133	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	133	0	0
T1	47639	0	0	0
T2	124217	0	0	0
T23	0	7	0	0
T33	1460	1	0	0
T34	2147	0	0	0
T35	1610	0	0	0
T36	1555	0	0	0
T37	1836	0	0	0
T38	2885	0	0	0
T53	13076	0	0	0
T54	1915	0	0	0
T59	0	1	0	0
T164	0	3	0	0
T173	0	2	0	0
T186	0	3	0	0
T198	0	1	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	133	0	0
T1	47639	0	0	0
T2	124217	0	0	0
T23	0	7	0	0
T33	1460	1	0	0
T34	2147	0	0	0
T35	1610	0	0	0
T36	1555	0	0	0
T37	1836	0	0	0
T38	2885	0	0	0
T53	13076	0	0	0
T54	1915	0	0	0
T59	0	1	0	0
T164	0	3	0	0
T173	0	2	0	0
T186	0	3	0	0
T198	0	1	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	39062799	140	0	0
StatusRise_A	39062799	140	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	140	0	0
T1	47639	0	0	0
T2	124217	0	0	0
T23	0	5	0	0
T33	1460	1	0	0
T34	2147	0	0	0
T35	1610	0	0	0
T36	1555	0	0	0
T37	1836	0	0	0
T38	2885	0	0	0
T53	13076	0	0	0
T54	1915	0	0	0
T59	0	4	0	0
T164	0	4	0	0
T173	0	1	0	0
T186	0	2	0	0
T198	0	2	0	0
T199	0	3	0	0
T200	0	2	0	0
T201	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39062799	140	0	0
T1	47639	0	0	0
T2	124217	0	0	0
T23	0	5	0	0
T33	1460	1	0	0
T34	2147	0	0	0
T35	1610	0	0	0
T36	1555	0	0	0
T37	1836	0	0	0
T38	2885	0	0	0
T53	13076	0	0	0
T54	1915	0	0	0
T59	0	4	0	0
T164	0	4	0	0
T173	0	1	0	0
T186	0	2	0	0
T198	0	2	0	0
T199	0	3	0	0
T200	0	2	0	0
T201	0	6	0	0