Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T53,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	794399822	32518	0	0
CgEnOn_A	794399822	23543	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794399822	32518	0	0
T1	412839	0	0	0
T2	647449	0	0	0
T4	3447	3	0	0
T5	26604	7	0	0
T6	10384	49	0	0
T23	0	41	0	0
T26	0	1	0	0
T28	0	1	0	0
T32	33004	6	0	0
T33	15234	13	0	0
T34	23156	3	0	0
T35	70428	3	0	0
T36	68604	3	0	0
T37	401646	3	0	0
T38	623074	10	0	0
T53	69860	0	0	0
T54	9077	0	0	0
T59	0	6	0	0
T164	0	15	0	0
T173	0	10	0	0
T186	0	15	0	0
T198	0	5	0	0
T199	0	15	0	0
T200	0	15	0	0
T201	0	30	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	794399822	23543	0	0
T1	507016	0	0	0
T2	647449	0	0	0
T5	26604	4	0	0
T6	10384	46	0	0
T21	0	3	0	0
T23	0	62	0	0
T26	0	4	0	0
T28	0	4	0	0
T29	0	4	0	0
T32	33004	3	0	0
T33	15234	10	0	0
T34	23156	0	0	0
T35	70428	0	0	0
T36	68604	0	0	0
T37	401646	0	0	0
T38	623074	7	0	0
T53	69860	0	0	0
T54	9077	0	0	0
T59	0	9	0	0
T113	0	10	0	0
T164	0	15	0	0
T173	0	10	0	0
T186	0	15	0	0
T198	0	5	0	0
T199	0	15	0	0
T200	0	15	0	0
T201	0	30	0	0
T202	0	7	0	0
T203	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T53,T23
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	33014455	153	0	0
CgEnOn_A	33014455	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33014455	153	0	0
T1	20906	0	0	0
T2	66931	0	0	0
T23	0	7	0	0
T33	626	1	0	0
T34	1023	0	0	0
T35	3300	0	0	0
T36	3339	0	0	0
T37	18835	0	0	0
T38	27648	0	0	0
T53	5728	0	0	0
T54	915	0	0	0
T59	0	1	0	0
T164	0	3	0	0
T173	0	2	0	0
T186	0	3	0	0
T198	0	1	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33014455	153	0	0
T1	20906	0	0	0
T2	66931	0	0	0
T23	0	7	0	0
T33	626	1	0	0
T34	1023	0	0	0
T35	3300	0	0	0
T36	3339	0	0	0
T37	18835	0	0	0
T38	27648	0	0	0
T53	5728	0	0	0
T54	915	0	0	0
T59	0	1	0	0
T164	0	3	0	0
T173	0	2	0	0
T186	0	3	0	0
T198	0	1	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T53,T23
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	16506839	154	0	0
CgEnOn_A	16506839	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16506839	154	0	0
T1	10453	0	0	0
T2	33466	0	0	0
T23	0	7	0	0
T33	313	1	0	0
T34	511	0	0	0
T35	1649	0	0	0
T36	1669	0	0	0
T37	9416	0	0	0
T38	13824	0	0	0
T53	2865	0	0	0
T54	457	0	0	0
T59	0	1	0	0
T164	0	3	0	0
T173	0	2	0	0
T186	0	3	0	0
T198	0	1	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16506839	153	0	0
T1	10453	0	0	0
T2	33466	0	0	0
T23	0	7	0	0
T33	313	1	0	0
T34	511	0	0	0
T35	1649	0	0	0
T36	1669	0	0	0
T37	9416	0	0	0
T38	13824	0	0	0
T53	2865	0	0	0
T54	457	0	0	0
T59	0	1	0	0
T164	0	3	0	0
T173	0	2	0	0
T186	0	3	0	0
T198	0	1	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T53,T23
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	16506839	154	0	0
CgEnOn_A	16506839	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16506839	154	0	0
T1	10453	0	0	0
T2	33466	0	0	0
T23	0	7	0	0
T33	313	1	0	0
T34	511	0	0	0
T35	1649	0	0	0
T36	1669	0	0	0
T37	9416	0	0	0
T38	13824	0	0	0
T53	2865	0	0	0
T54	457	0	0	0
T59	0	1	0	0
T164	0	3	0	0
T173	0	2	0	0
T186	0	3	0	0
T198	0	1	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16506839	153	0	0
T1	10453	0	0	0
T2	33466	0	0	0
T23	0	7	0	0
T33	313	1	0	0
T34	511	0	0	0
T35	1649	0	0	0
T36	1669	0	0	0
T37	9416	0	0	0
T38	13824	0	0	0
T53	2865	0	0	0
T54	457	0	0	0
T59	0	1	0	0
T164	0	3	0	0
T173	0	2	0	0
T186	0	3	0	0
T198	0	1	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T53,T23
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	16506839	154	0	0
CgEnOn_A	16506839	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16506839	154	0	0
T1	10453	0	0	0
T2	33466	0	0	0
T23	0	7	0	0
T33	313	1	0	0
T34	511	0	0	0
T35	1649	0	0	0
T36	1669	0	0	0
T37	9416	0	0	0
T38	13824	0	0	0
T53	2865	0	0	0
T54	457	0	0	0
T59	0	1	0	0
T164	0	3	0	0
T173	0	2	0	0
T186	0	3	0	0
T198	0	1	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16506839	153	0	0
T1	10453	0	0	0
T2	33466	0	0	0
T23	0	7	0	0
T33	313	1	0	0
T34	511	0	0	0
T35	1649	0	0	0
T36	1669	0	0	0
T37	9416	0	0	0
T38	13824	0	0	0
T53	2865	0	0	0
T54	457	0	0	0
T59	0	1	0	0
T164	0	3	0	0
T173	0	2	0	0
T186	0	3	0	0
T198	0	1	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T53,T23
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	67850313	153	0	0
CgEnOn_A	67850313	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67850313	153	0	0
T1	41879	0	0	0
T2	133983	0	0	0
T23	0	7	0	0
T33	1372	1	0	0
T34	2062	0	0	0
T35	6187	0	0	0
T36	5973	0	0	0
T37	35276	0	0	0
T38	55403	0	0	0
T53	15498	0	0	0
T54	1895	0	0	0
T59	0	1	0	0
T164	0	3	0	0
T173	0	2	0	0
T186	0	3	0	0
T198	0	1	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67850313	135	0	0
T1	41879	0	0	0
T2	133983	0	0	0
T23	0	7	0	0
T33	1372	1	0	0
T34	2062	0	0	0
T35	6187	0	0	0
T36	5973	0	0	0
T37	35276	0	0	0
T38	55403	0	0	0
T53	15498	0	0	0
T54	1895	0	0	0
T59	0	1	0	0
T164	0	3	0	0
T173	0	2	0	0
T186	0	3	0	0
T198	0	1	0	0
T199	0	3	0	0
T200	0	3	0	0
T201	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T53,T23
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	75706418	137	0	0
CgEnOn_A	75706418	133	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706418	137	0	0
T1	49626	0	0	0
T2	139571	0	0	0
T23	0	6	0	0
T33	1437	2	0	0
T34	2147	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36747	0	0	0
T38	57712	0	0	0
T53	16145	0	0	0
T54	1974	0	0	0
T59	0	1	0	0
T164	0	4	0	0
T173	0	3	0	0
T186	0	3	0	0
T198	0	2	0	0
T199	0	4	0	0
T200	0	3	0	0
T201	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706418	133	0	0
T1	49626	0	0	0
T2	139571	0	0	0
T23	0	6	0	0
T33	1437	2	0	0
T34	2147	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36747	0	0	0
T38	57712	0	0	0
T53	16145	0	0	0
T54	1974	0	0	0
T59	0	1	0	0
T164	0	4	0	0
T173	0	3	0	0
T186	0	3	0	0
T198	0	2	0	0
T199	0	4	0	0
T200	0	3	0	0
T201	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T53,T23
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	75706418	137	0	0
CgEnOn_A	75706418	133	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706418	137	0	0
T1	49626	0	0	0
T2	139571	0	0	0
T23	0	6	0	0
T33	1437	2	0	0
T34	2147	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36747	0	0	0
T38	57712	0	0	0
T53	16145	0	0	0
T54	1974	0	0	0
T59	0	1	0	0
T164	0	4	0	0
T173	0	3	0	0
T186	0	3	0	0
T198	0	2	0	0
T199	0	4	0	0
T200	0	3	0	0
T201	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706418	133	0	0
T1	49626	0	0	0
T2	139571	0	0	0
T23	0	6	0	0
T33	1437	2	0	0
T34	2147	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36747	0	0	0
T38	57712	0	0	0
T53	16145	0	0	0
T54	1974	0	0	0
T59	0	1	0	0
T164	0	4	0	0
T173	0	3	0	0
T186	0	3	0	0
T198	0	2	0	0
T199	0	4	0	0
T200	0	3	0	0
T201	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T53,T23
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	36202211	148	0	0
CgEnOn_A	36202211	142	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36202211	148	0	0
T1	20939	0	0	0
T2	66995	0	0	0
T23	0	5	0	0
T33	682	1	0	0
T34	1030	0	0	0
T35	3094	0	0	0
T36	2986	0	0	0
T37	17639	0	0	0
T38	27702	0	0	0
T53	7749	0	0	0
T54	948	0	0	0
T59	0	4	0	0
T164	0	4	0	0
T173	0	1	0	0
T186	0	2	0	0
T198	0	2	0	0
T199	0	3	0	0
T200	0	2	0	0
T201	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36202211	142	0	0
T1	20939	0	0	0
T2	66995	0	0	0
T23	0	5	0	0
T33	682	1	0	0
T34	1030	0	0	0
T35	3094	0	0	0
T36	2986	0	0	0
T37	17639	0	0	0
T38	27702	0	0	0
T53	7749	0	0	0
T54	948	0	0	0
T59	0	4	0	0
T164	0	4	0	0
T173	0	1	0	0
T186	0	2	0	0
T198	0	2	0	0
T199	0	3	0	0
T200	0	2	0	0
T201	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T23,T59
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	16506839	5433	0	0
CgEnOn_A	16506839	3211	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16506839	5433	0	0
T4	410	1	0	0
T5	1031	2	0	0
T6	375	16	0	0
T32	1280	1	0	0
T33	313	2	0	0
T34	511	1	0	0
T35	1649	1	0	0
T36	1669	1	0	0
T37	9416	1	0	0
T38	13824	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	16506839	3211	0	0
T1	10453	0	0	0
T5	1031	1	0	0
T6	375	15	0	0
T21	0	1	0	0
T23	0	7	0	0
T26	0	1	0	0
T28	0	1	0	0
T32	1280	0	0	0
T33	313	1	0	0
T34	511	0	0	0
T35	1649	0	0	0
T36	1669	0	0	0
T37	9416	0	0	0
T38	13824	0	0	0
T59	0	1	0	0
T202	0	3	0	0
T203	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T23,T59
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	33014455	5482	0	0
CgEnOn_A	33014455	3260	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33014455	5482	0	0
T4	820	1	0	0
T5	2062	2	0	0
T6	750	18	0	0
T32	2561	1	0	0
T33	626	2	0	0
T34	1023	1	0	0
T35	3300	1	0	0
T36	3339	1	0	0
T37	18835	1	0	0
T38	27648	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33014455	3260	0	0
T1	20906	0	0	0
T5	2062	1	0	0
T6	750	17	0	0
T21	0	1	0	0
T23	0	7	0	0
T26	0	1	0	0
T28	0	1	0	0
T32	2561	0	0	0
T33	626	1	0	0
T34	1023	0	0	0
T35	3300	0	0	0
T36	3339	0	0	0
T37	18835	0	0	0
T38	27648	0	0	0
T59	0	1	0	0
T202	0	2	0	0
T203	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T23,T59
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	67850313	5481	0	0
CgEnOn_A	67850313	3241	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67850313	5481	0	0
T4	1478	1	0	0
T5	4149	2	0	0
T6	1634	15	0	0
T32	5146	1	0	0
T33	1372	2	0	0
T34	2062	1	0	0
T35	6187	1	0	0
T36	5973	1	0	0
T37	35276	1	0	0
T38	55403	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67850313	3241	0	0
T1	41879	0	0	0
T5	4149	1	0	0
T6	1634	14	0	0
T21	0	1	0	0
T23	0	7	0	0
T26	0	1	0	0
T28	0	1	0	0
T32	5146	0	0	0
T33	1372	1	0	0
T34	2062	0	0	0
T35	6187	0	0	0
T36	5973	0	0	0
T37	35276	0	0	0
T38	55403	0	0	0
T59	0	1	0	0
T202	0	2	0	0
T203	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T23,T59
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	36202211	5483	0	0
CgEnOn_A	36202211	3243	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36202211	5483	0	0
T4	739	1	0	0
T5	2074	2	0	0
T6	817	15	0	0
T32	2573	1	0	0
T33	682	2	0	0
T34	1030	1	0	0
T35	3094	1	0	0
T36	2986	1	0	0
T37	17639	1	0	0
T38	27702	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36202211	3243	0	0
T1	20939	0	0	0
T5	2074	1	0	0
T6	817	14	0	0
T21	0	1	0	0
T23	0	5	0	0
T26	0	1	0	0
T28	0	1	0	0
T32	2573	0	0	0
T33	682	1	0	0
T34	1030	0	0	0
T35	3094	0	0	0
T36	2986	0	0	0
T37	17639	0	0	0
T38	27702	0	0	0
T59	0	4	0	0
T202	0	3	0	0
T203	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T53,T23
1	0	Covered	T5,T32,T38
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	75706418	2415	0	0
CgEnOn_A	75706418	2411	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706418	2415	0	0
T1	49626	0	0	0
T5	4322	1	0	0
T6	1702	0	0	0
T23	0	6	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	4	0	0
T32	5361	3	0	0
T33	1437	2	0	0
T34	2147	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36747	0	0	0
T38	57712	7	0	0
T59	0	1	0	0
T113	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706418	2411	0	0
T1	49626	0	0	0
T5	4322	1	0	0
T6	1702	0	0	0
T23	0	6	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	4	0	0
T32	5361	3	0	0
T33	1437	2	0	0
T34	2147	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36747	0	0	0
T38	57712	7	0	0
T59	0	1	0	0
T113	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T53,T23
1	0	Covered	T5,T32,T38
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	75706418	2366	0	0
CgEnOn_A	75706418	2362	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706418	2366	0	0
T1	49626	0	0	0
T5	4322	1	0	0
T6	1702	0	0	0
T23	0	6	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	4	0	0
T32	5361	3	0	0
T33	1437	2	0	0
T34	2147	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36747	0	0	0
T38	57712	7	0	0
T59	0	1	0	0
T113	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706418	2362	0	0
T1	49626	0	0	0
T5	4322	1	0	0
T6	1702	0	0	0
T23	0	6	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	4	0	0
T32	5361	3	0	0
T33	1437	2	0	0
T34	2147	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36747	0	0	0
T38	57712	7	0	0
T59	0	1	0	0
T113	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T53,T23
1	0	Covered	T5,T32,T38
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	75706418	2354	0	0
CgEnOn_A	75706418	2350	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706418	2354	0	0
T1	49626	0	0	0
T5	4322	1	0	0
T6	1702	0	0	0
T23	0	6	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	5	0	0
T32	5361	3	0	0
T33	1437	2	0	0
T34	2147	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36747	0	0	0
T38	57712	9	0	0
T59	0	1	0	0
T113	0	11	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706418	2350	0	0
T1	49626	0	0	0
T5	4322	1	0	0
T6	1702	0	0	0
T23	0	6	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	5	0	0
T32	5361	3	0	0
T33	1437	2	0	0
T34	2147	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36747	0	0	0
T38	57712	9	0	0
T59	0	1	0	0
T113	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T53,T23
1	0	Covered	T5,T32,T38
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	75706418	2314	0	0
CgEnOn_A	75706418	2310	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706418	2314	0	0
T1	49626	0	0	0
T5	4322	1	0	0
T6	1702	0	0	0
T23	0	6	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	3	0	0
T32	5361	2	0	0
T33	1437	2	0	0
T34	2147	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36747	0	0	0
T38	57712	13	0	0
T59	0	1	0	0
T113	0	13	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	75706418	2310	0	0
T1	49626	0	0	0
T5	4322	1	0	0
T6	1702	0	0	0
T23	0	6	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	3	0	0
T32	5361	2	0	0
T33	1437	2	0	0
T34	2147	0	0	0
T35	6445	0	0	0
T36	6222	0	0	0
T37	36747	0	0	0
T38	57712	13	0	0
T59	0	1	0	0
T113	0	13	0	0