| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 | 
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| clkmgr_reg_block.io_div2_meas_ctrl_shadowed.hi_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| clkmgr_reg_block.io_div2_meas_ctrl_shadowed.lo_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| clkmgr_reg_block.io_div4_meas_ctrl_shadowed.hi_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| clkmgr_reg_block.io_div4_meas_ctrl_shadowed.lo_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| clkmgr_reg_block.io_meas_ctrl_shadowed.hi_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| clkmgr_reg_block.io_meas_ctrl_shadowed.lo_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| clkmgr_reg_block.main_meas_ctrl_shadowed.hi_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| clkmgr_reg_block.main_meas_ctrl_shadowed.lo_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| clkmgr_reg_block.usb_meas_ctrl_shadowed.hi_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| clkmgr_reg_block.usb_meas_ctrl_shadowed.lo_shadowed_errs_cov | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 2 | 0 | 2 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 2 | 0 | 2 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 2 | 0 | 2 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 2 | 0 | 2 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 2 | 0 | 2 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 2 | 0 | 2 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 2 | 0 | 2 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 2 | 0 | 2 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 2 | 0 | 2 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 2 | 0 | 2 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_storage_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | |
| cp_update_err | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 0 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 15242 | 1 | T1 | 18 | T2 | 32 | T3 | 28 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 38 | 1 | T75 | 3 | T76 | 1 | T78 | 2 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 15242 | 1 | T1 | 18 | T2 | 32 | T3 | 28 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 35 | 1 | T74 | 1 | T75 | 2 | T76 | 1 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 15317 | 1 | T1 | 18 | T2 | 32 | T3 | 28 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 42 | 1 | T75 | 2 | T76 | 1 | T78 | 4 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 15317 | 1 | T1 | 18 | T2 | 32 | T3 | 28 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 37 | 1 | T74 | 1 | T75 | 1 | T78 | 4 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 15380 | 1 | T1 | 18 | T2 | 32 | T3 | 28 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 36 | 1 | T77 | 1 | T74 | 1 | T75 | 2 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 15380 | 1 | T1 | 18 | T2 | 32 | T3 | 28 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 39 | 1 | T77 | 1 | T74 | 2 | T75 | 1 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 15440 | 1 | T1 | 18 | T2 | 32 | T3 | 28 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 40 | 1 | T77 | 1 | T74 | 2 | T75 | 4 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 15440 | 1 | T1 | 18 | T2 | 32 | T3 | 28 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 34 | 1 | T74 | 2 | T75 | 3 | T76 | 1 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 15292 | 1 | T1 | 18 | T2 | 32 | T3 | 28 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 45 | 1 | T74 | 2 | T75 | 2 | T76 | 1 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| storage_err | 15292 | 1 | T1 | 18 | T2 | 32 | T3 | 28 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 1 | 0 | 1 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| update_err | 37 | 1 | T75 | 1 | T78 | 1 | T80 | 3 | 
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |