Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	200384	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

468343

1

T4

25

T5

20

T6

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	194929	1			T4	42		T5	20		T29	56
values[0x0]	224855	1			T4	19		T5	19		T6	14
values[0x1]	248943	1			T4	20		T5	22		T6	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	138907	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

529820

1

T4

31

T5

24

T6

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2279	1			T29	2		T30	1		T32	1
valid_sources[0x01]	2442	1			T73	2		T22	1		T50	4
valid_sources[0x02]	2423	1			T4	1		T1	1		T55	1
valid_sources[0x03]	2526	1			T1	3		T57	1		T71	3
valid_sources[0x04]	3315	1			T31	1		T32	1		T1	1
valid_sources[0x05]	2214	1			T32	1		T1	1		T22	2
valid_sources[0x06]	2054	1			T4	1		T1	1		T24	2
valid_sources[0x07]	1932	1			T31	3		T73	1		T22	1
valid_sources[0x08]	2110	1			T56	1		T57	1		T48	7
valid_sources[0x09]	2834	1			T29	1		T55	1		T57	2
valid_sources[0x0a]	2212	1			T30	1		T31	1		T57	1
valid_sources[0x0b]	2254	1			T32	3		T1	1		T20	1
valid_sources[0x0c]	2859	1			T45	5		T46	1		T48	12
valid_sources[0x0d]	2592	1			T29	1		T1	1		T57	1
valid_sources[0x0e]	2950	1			T4	1		T32	1		T1	1
valid_sources[0x0f]	2364	1			T29	2		T32	1		T73	1
valid_sources[0x10]	2486	1			T31	1		T55	2		T57	1
valid_sources[0x11]	2715	1			T1	1		T57	1		T69	25
valid_sources[0x12]	2492	1			T57	1		T44	1		T48	4
valid_sources[0x13]	2635	1			T4	1		T30	1		T1	1
valid_sources[0x14]	3001	1			T4	1		T32	1		T51	19
valid_sources[0x15]	2595	1			T32	1		T56	1		T73	1
valid_sources[0x16]	2715	1			T1	2		T55	1		T22	1
valid_sources[0x17]	2861	1			T70	1		T93	1		T11	13
valid_sources[0x18]	2418	1			T29	1		T1	1		T55	3
valid_sources[0x19]	2510	1			T29	1		T32	2		T56	6
valid_sources[0x1a]	2157	1			T29	1		T32	2		T1	1
valid_sources[0x1b]	2408	1			T1	2		T57	1		T11	17
valid_sources[0x1c]	3339	1			T1	1		T57	1		T10	11
valid_sources[0x1d]	2317	1			T5	61		T32	1		T1	1
valid_sources[0x1e]	3059	1			T29	1		T11	2		T10	7
valid_sources[0x1f]	2847	1			T1	1		T55	2		T48	2
valid_sources[0x20]	2185	1			T32	1		T1	1		T57	1
valid_sources[0x21]	2515	1			T4	1		T32	1		T57	1
valid_sources[0x22]	2146	1			T6	23		T31	1		T1	1
valid_sources[0x23]	1882	1			T1	2		T93	1		T48	5
valid_sources[0x24]	2025	1			T4	1		T29	2		T32	1
valid_sources[0x25]	2984	1			T31	3		T57	3		T22	1
valid_sources[0x26]	3056	1			T1	3		T57	1		T48	4
valid_sources[0x27]	1938	1			T32	1		T57	1		T73	1
valid_sources[0x28]	2718	1			T4	1		T1	2		T93	2
valid_sources[0x29]	2030	1			T29	2		T1	1		T55	1
valid_sources[0x2a]	3171	1			T30	1		T1	1		T57	1
valid_sources[0x2b]	2128	1			T56	1		T22	1		T11	13
valid_sources[0x2c]	2381	1			T1	1		T55	1		T11	6
valid_sources[0x2d]	2084	1			T70	1		T44	1		T50	2
valid_sources[0x2e]	2139	1			T1	2		T57	1		T11	1
valid_sources[0x2f]	3062	1			T4	1		T48	3		T50	1
valid_sources[0x30]	5370	1			T11	3		T172	1		T95	1
valid_sources[0x31]	2231	1			T31	3		T50	8		T203	2
valid_sources[0x32]	2183	1			T32	2		T93	1		T11	14
valid_sources[0x33]	2228	1			T31	1		T32	1		T54	1
valid_sources[0x34]	2890	1			T32	1		T1	2		T46	1
valid_sources[0x35]	2603	1			T1	1		T55	1		T57	1
valid_sources[0x36]	2340	1			T1	2		T57	1		T22	2
valid_sources[0x37]	3135	1			T1	2		T73	1		T50	1
valid_sources[0x38]	2613	1			T51	3		T73	1		T11	2
valid_sources[0x39]	3253	1			T29	2		T1	1		T27	2
valid_sources[0x3a]	2937	1			T30	2		T54	1		T56	2
valid_sources[0x3b]	3629	1			T53	6		T70	1		T11	24
valid_sources[0x3c]	2662	1			T29	4		T32	1		T1	1
valid_sources[0x3d]	2106	1			T1	2		T55	2		T22	1
valid_sources[0x3e]	2802	1			T1	2		T93	1		T44	1
valid_sources[0x3f]	2285	1			T32	1		T56	1		T24	7
valid_sources[0x40]	3495	1			T29	1		T1	1		T57	1
valid_sources[0x41]	2279	1			T32	2		T1	3		T57	2
valid_sources[0x42]	2883	1			T4	2		T29	1		T1	1
valid_sources[0x43]	1964	1			T57	1		T20	1		T93	2
valid_sources[0x44]	2367	1			T4	1		T29	2		T1	1
valid_sources[0x45]	2277	1			T4	2		T31	1		T1	1
valid_sources[0x46]	2537	1			T1	1		T57	2		T48	10
valid_sources[0x47]	2388	1			T1	2		T55	2		T56	1
valid_sources[0x48]	4515	1			T29	1		T32	1		T1	2
valid_sources[0x49]	3700	1			T4	1		T32	1		T57	1
valid_sources[0x4a]	2289	1			T1	1		T57	1		T10	1
valid_sources[0x4b]	2482	1			T22	2		T48	5		T12	1
valid_sources[0x4c]	3034	1			T1	2		T57	1		T11	6
valid_sources[0x4d]	3156	1			T4	1		T29	1		T22	1
valid_sources[0x4e]	2476	1			T4	3		T1	1		T57	1
valid_sources[0x4f]	2422	1			T29	4		T31	1		T27	1
valid_sources[0x50]	2239	1			T29	1		T31	1		T32	3
valid_sources[0x51]	2624	1			T32	1		T1	1		T73	2
valid_sources[0x52]	3253	1			T32	2		T11	4		T10	4
valid_sources[0x53]	2733	1			T29	2		T1	2		T56	2
valid_sources[0x54]	2114	1			T4	1		T29	1		T55	1
valid_sources[0x55]	2565	1			T4	1		T57	1		T22	1
valid_sources[0x56]	2681	1			T29	1		T30	1		T1	1
valid_sources[0x57]	3347	1			T30	3		T1	2		T54	1
valid_sources[0x58]	1836	1			T1	2		T57	1		T26	84
valid_sources[0x59]	2950	1			T4	2		T32	1		T55	1
valid_sources[0x5a]	2396	1			T29	2		T1	2		T55	1
valid_sources[0x5b]	2307	1			T4	1		T32	1		T1	3
valid_sources[0x5c]	2236	1			T1	1		T57	1		T22	1
valid_sources[0x5d]	2536	1			T48	5		T50	8		T12	1
valid_sources[0x5e]	2580	1			T29	1		T1	2		T27	1
valid_sources[0x5f]	2706	1			T30	1		T31	8		T22	2
valid_sources[0x60]	2614	1			T1	1		T57	1		T73	1
valid_sources[0x61]	2258	1			T29	1		T44	1		T50	8
valid_sources[0x62]	2476	1			T57	1		T22	1		T23	37
valid_sources[0x63]	2874	1			T32	1		T1	1		T44	2
valid_sources[0x64]	2522	1			T31	3		T57	4		T11	6
valid_sources[0x65]	2209	1			T1	1		T70	1		T11	4
valid_sources[0x66]	2958	1			T29	1		T1	2		T55	1
valid_sources[0x67]	2381	1			T1	1		T57	1		T93	1
valid_sources[0x68]	1893	1			T30	1		T32	2		T1	1
valid_sources[0x69]	5301	1			T4	1		T29	1		T1	1
valid_sources[0x6a]	4881	1			T32	1		T1	1		T53	10
valid_sources[0x6b]	2478	1			T29	1		T32	2		T93	1
valid_sources[0x6c]	2737	1			T32	1		T20	1		T22	1
valid_sources[0x6d]	3022	1			T4	1		T70	1		T71	6
valid_sources[0x6e]	2030	1			T56	3		T11	15		T50	3
valid_sources[0x6f]	2496	1			T32	2		T53	7		T57	1
valid_sources[0x70]	2478	1			T30	2		T32	2		T1	1
valid_sources[0x71]	3794	1			T29	1		T1	1		T20	1
valid_sources[0x72]	2591	1			T29	1		T1	3		T54	1
valid_sources[0x73]	3706	1			T51	2		T56	3		T57	1
valid_sources[0x74]	2236	1			T30	2		T32	1		T1	1
valid_sources[0x75]	1944	1			T4	1		T29	2		T32	2
valid_sources[0x76]	2254	1			T29	3		T1	1		T57	2
valid_sources[0x77]	2721	1			T4	1		T1	1		T70	1
valid_sources[0x78]	2153	1			T29	2		T1	1		T11	3
valid_sources[0x79]	2795	1			T1	2		T54	1		T22	2
valid_sources[0x7a]	3149	1			T29	2		T57	1		T73	1
valid_sources[0x7b]	2421	1			T32	1		T1	1		T57	2
valid_sources[0x7c]	2166	1			T55	1		T48	4		T10	2
valid_sources[0x7d]	2412	1			T4	2		T32	2		T1	1
valid_sources[0x7e]	3195	1			T4	1		T53	9		T54	2
valid_sources[0x7f]	2648	1			T4	1		T29	1		T1	1
valid_sources[0x80]	2810	1			T4	1		T22	1		T93	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

130964

1

T4

15

T5

9

T29

29

values[0x0]

all_enables

biggest_size

181119

1

T4

8

T5

6

T6

6

values[0x1]

all_enables

biggest_size

156260

1

T4

2

T5

5

T6

3