Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T28
0	1	Covered	T6,T56,T24
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T53
1	0	Covered	T28,T61,T25
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	166296793	7352	0	0
GateOpen_A	166296793	13955	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166296793	7352	0	0
T1	215678	0	0	0
T4	5128	4	0	0
T5	25272	0	0	0
T6	36218	20	0	0
T22	0	4	0	0
T24	0	22	0	0
T25	0	19	0	0
T28	9508	21	0	0
T29	8720	0	0	0
T30	8475	0	0	0
T31	5615	0	0	0
T32	6663	0	0	0
T33	9344	0	0	0
T47	0	4	0	0
T53	0	3	0	0
T56	0	29	0	0
T61	0	14	0	0
T194	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166296793	13955	0	0
T1	215678	4	0	0
T4	5128	4	0	0
T5	25272	4	0	0
T6	36218	24	0	0
T28	9508	25	0	0
T29	8720	4	0	0
T30	8475	4	0	0
T31	5615	4	0	0
T32	6663	4	0	0
T33	9344	0	0	0
T53	0	3	0	0
T54	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T28
0	1	Covered	T6,T56,T24
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T55
1	0	Covered	T28,T61,T25
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	17948783	1769	0	0
GateOpen_A	17948783	3415	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17948783	1769	0	0
T1	23949	0	0	0
T4	564	1	0	0
T5	3052	0	0	0
T6	4016	5	0	0
T22	0	1	0	0
T24	0	4	0	0
T25	0	5	0	0
T28	1056	5	0	0
T29	956	0	0	0
T30	958	0	0	0
T31	639	0	0	0
T32	730	0	0	0
T33	1063	0	0	0
T47	0	1	0	0
T56	0	6	0	0
T61	0	3	0	0
T194	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17948783	3415	0	0
T1	23949	1	0	0
T4	564	1	0	0
T5	3052	1	0	0
T6	4016	6	0	0
T28	1056	6	0	0
T29	956	1	0	0
T30	958	1	0	0
T31	639	1	0	0
T32	730	1	0	0
T33	1063	0	0	0
T54	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T28
0	1	Covered	T6,T56,T24
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T53
1	0	Covered	T28,T61,T25
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	35898102	1872	0	0
GateOpen_A	35898102	3518	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35898102	1872	0	0
T1	47897	0	0	0
T4	1127	1	0	0
T5	6107	0	0	0
T6	8031	6	0	0
T22	0	1	0	0
T24	0	6	0	0
T25	0	5	0	0
T28	2112	5	0	0
T29	1911	0	0	0
T30	1917	0	0	0
T31	1280	0	0	0
T32	1459	0	0	0
T33	2126	0	0	0
T47	0	1	0	0
T53	0	1	0	0
T56	0	7	0	0
T61	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35898102	3518	0	0
T1	47897	1	0	0
T4	1127	1	0	0
T5	6107	1	0	0
T6	8031	7	0	0
T28	2112	6	0	0
T29	1911	1	0	0
T30	1917	1	0	0
T31	1280	1	0	0
T32	1459	1	0	0
T33	2126	0	0	0
T53	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T28
0	1	Covered	T6,T56,T24
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T53
1	0	Covered	T28,T61,T25
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	73312146	1862	0	0
GateOpen_A	73312146	3517	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73312146	1862	0	0
T1	95886	0	0	0
T4	2291	1	0	0
T5	10742	0	0	0
T6	16114	5	0	0
T22	0	1	0	0
T24	0	6	0	0
T25	0	5	0	0
T28	4249	5	0	0
T29	3902	0	0	0
T30	3733	0	0	0
T31	2464	0	0	0
T32	2983	0	0	0
T33	4103	0	0	0
T47	0	1	0	0
T53	0	1	0	0
T56	0	8	0	0
T61	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73312146	3517	0	0
T1	95886	1	0	0
T4	2291	1	0	0
T5	10742	1	0	0
T6	16114	6	0	0
T28	4249	6	0	0
T29	3902	1	0	0
T30	3733	1	0	0
T31	2464	1	0	0
T32	2983	1	0	0
T33	4103	0	0	0
T53	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T28
0	1	Covered	T6,T56,T24
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T53
1	0	Covered	T28,T61,T25
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	39137762	1849	0	0
GateOpen_A	39137762	3505	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39137762	1849	0	0
T1	47946	0	0	0
T4	1146	1	0	0
T5	5371	0	0	0
T6	8057	4	0	0
T22	0	1	0	0
T24	0	6	0	0
T25	0	4	0	0
T28	2091	6	0	0
T29	1951	0	0	0
T30	1867	0	0	0
T31	1232	0	0	0
T32	1491	0	0	0
T33	2052	0	0	0
T47	0	1	0	0
T53	0	1	0	0
T56	0	8	0	0
T61	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39137762	3505	0	0
T1	47946	1	0	0
T4	1146	1	0	0
T5	5371	1	0	0
T6	8057	5	0	0
T28	2091	7	0	0
T29	1951	1	0	0
T30	1867	1	0	0
T31	1232	1	0	0
T32	1491	1	0	0
T33	2052	0	0	0
T53	0	1	0	0