Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	192781230	36584	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192781230	36584	0	0
T3	819545	426	0	0
T9	0	79	0	0
T10	0	121	0	0
T12	0	88	0	0
T13	0	93	0	0
T14	0	268	0	0
T15	0	52	0	0
T16	0	147	0	0
T17	0	188	0	0
T18	0	986	0	0
T19	50075	0	0	0
T20	8410	0	0	0
T21	299000	0	0	0
T22	5025	0	0	0
T23	10295	0	0	0
T24	7880	0	0	0
T25	5170	0	0	0
T26	8730	0	0	0
T27	7430	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38556246	5326	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	5326	0	0
T3	163909	55	0	0
T9	0	11	0	0
T10	0	16	0	0
T12	0	11	0	0
T13	0	15	0	0
T14	0	39	0	0
T15	0	9	0	0
T16	0	24	0	0
T17	0	28	0	0
T18	0	145	0	0
T19	10015	0	0	0
T20	1682	0	0	0
T21	59800	0	0	0
T22	1005	0	0	0
T23	2059	0	0	0
T24	1576	0	0	0
T25	1034	0	0	0
T26	1746	0	0	0
T27	1486	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38556246	5199	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	5199	0	0
T3	163909	61	0	0
T9	0	11	0	0
T10	0	17	0	0
T12	0	12	0	0
T13	0	15	0	0
T14	0	39	0	0
T15	0	8	0	0
T16	0	23	0	0
T17	0	24	0	0
T18	0	122	0	0
T19	10015	0	0	0
T20	1682	0	0	0
T21	59800	0	0	0
T22	1005	0	0	0
T23	2059	0	0	0
T24	1576	0	0	0
T25	1034	0	0	0
T26	1746	0	0	0
T27	1486	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38556246	7342	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	7342	0	0
T3	163909	87	0	0
T9	0	16	0	0
T10	0	24	0	0
T12	0	18	0	0
T13	0	19	0	0
T14	0	60	0	0
T15	0	11	0	0
T16	0	30	0	0
T17	0	36	0	0
T18	0	195	0	0
T19	10015	0	0	0
T20	1682	0	0	0
T21	59800	0	0	0
T22	1005	0	0	0
T23	2059	0	0	0
T24	1576	0	0	0
T25	1034	0	0	0
T26	1746	0	0	0
T27	1486	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38556246	7367	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	7367	0	0
T3	163909	83	0	0
T9	0	16	0	0
T10	0	24	0	0
T12	0	19	0	0
T13	0	19	0	0
T14	0	52	0	0
T15	0	11	0	0
T16	0	30	0	0
T17	0	40	0	0
T18	0	203	0	0
T19	10015	0	0	0
T20	1682	0	0	0
T21	59800	0	0	0
T22	1005	0	0	0
T23	2059	0	0	0
T24	1576	0	0	0
T25	1034	0	0	0
T26	1746	0	0	0
T27	1486	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38556246	11350	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	11350	0	0
T3	163909	140	0	0
T9	0	25	0	0
T10	0	40	0	0
T12	0	28	0	0
T13	0	25	0	0
T14	0	78	0	0
T15	0	13	0	0
T16	0	40	0	0
T17	0	60	0	0
T18	0	321	0	0
T19	10015	0	0	0
T20	1682	0	0	0
T21	59800	0	0	0
T22	1005	0	0	0
T23	2059	0	0	0
T24	1576	0	0	0
T25	1034	0	0	0
T26	1746	0	0	0
T27	1486	0	0	0