Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

22                      
23         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T55,T2,T19

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	38556246	35787322	0	0
AllClkBypReqTrue_A	38556246	85115	0	0
IoClkBypReqFalse_A	38556246	35735435	0	2415
IoClkBypReqTrue_A	38556246	132414	0	0
LcClkBypAckFalse_A	38556246	35795618	0	0
LcClkBypAckTrue_A	38556246	76819	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	35787322	0	0
T1	27970	27924	0	0
T4	2386	2273	0	0
T5	2461	2044	0	0
T6	838	829	0	0
T28	1164	1144	0	0
T29	2031	1932	0	0
T30	1867	1737	0	0
T31	2566	2322	0	0
T32	2982	2847	0	0
T33	1068	996	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	85115	0	0
T1	27970	0	0	0
T5	2461	360	0	0
T6	838	0	0	0
T23	0	244	0	0
T28	1164	0	0	0
T29	2031	0	0	0
T30	1867	27	0	0
T31	2566	160	0	0
T32	2982	0	0	0
T33	1068	43	0	0
T51	2327	384	0	0
T52	0	64	0	0
T70	0	83	0	0
T72	0	176	0	0
T73	0	180	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	35735435	0	2415
T1	27970	27922	0	3
T4	2386	2271	0	3
T5	2461	1822	0	3
T6	838	827	0	3
T28	1164	1142	0	3
T29	2031	1930	0	3
T30	1867	1429	0	3
T31	2566	2372	0	3
T32	2982	2845	0	3
T33	1068	963	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	132414	0	0
T1	27970	0	0	0
T5	2461	580	0	0
T6	838	0	0	0
T28	1164	0	0	0
T29	2031	0	0	0
T30	1867	333	0	0
T31	2566	108	0	0
T32	2982	0	0	0
T33	1068	74	0	0
T51	2327	516	0	0
T52	0	26	0	0
T69	0	187	0	0
T70	0	113	0	0
T72	0	37	0	0
T73	0	366	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	35795618	0	0
T1	27970	27924	0	0
T4	2386	2273	0	0
T5	2461	2118	0	0
T6	838	829	0	0
T28	1164	1144	0	0
T29	2031	1932	0	0
T30	1867	1662	0	0
T31	2566	2402	0	0
T32	2982	2847	0	0
T33	1068	988	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	76819	0	0
T1	27970	0	0	0
T5	2461	286	0	0
T6	838	0	0	0
T23	0	221	0	0
T28	1164	0	0	0
T29	2031	0	0	0
T30	1867	102	0	0
T31	2566	80	0	0
T32	2982	0	0	0
T33	1068	51	0	0
T51	2327	199	0	0
T69	0	21	0	0
T70	0	89	0	0
T72	0	1	0	0
T73	0	183	0	0