Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	326795008	8845	0	0
TransStop_A	326795008	4625	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326795008	8845	0	0
T1	399540	0	0	0
T4	9548	4	0	0
T5	44760	0	0	0
T6	67144	0	0	0
T22	0	4	0	0
T26	0	24	0	0
T28	16964	0	0	0
T29	16256	26	0	0
T30	15556	0	0	0
T31	10268	0	0	0
T32	12428	28	0	0
T33	17100	0	0	0
T47	0	4	0	0
T53	0	4	0	0
T57	0	32	0	0
T71	0	33	0	0
T93	0	24	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	326795008	4625	0	0
T1	399540	0	0	0
T4	9548	4	0	0
T5	44760	0	0	0
T6	67144	0	0	0
T22	0	4	0	0
T26	0	16	0	0
T28	16964	0	0	0
T29	16256	14	0	0
T30	15556	0	0	0
T31	10268	0	0	0
T32	12428	14	0	0
T33	17100	0	0	0
T47	0	4	0	0
T53	0	4	0	0
T57	0	12	0	0
T71	0	12	0	0
T93	0	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	81698752	2201	0	0
TransStop_A	81698752	1175	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698752	2201	0	0
T1	99885	0	0	0
T4	2387	1	0	0
T5	11190	0	0	0
T6	16786	0	0	0
T22	0	1	0	0
T26	0	7	0	0
T28	4241	0	0	0
T29	4064	10	0	0
T30	3889	0	0	0
T31	2567	0	0	0
T32	3107	7	0	0
T33	4275	0	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	0	6	0	0
T71	0	9	0	0
T93	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698752	1175	0	0
T1	99885	0	0	0
T4	2387	1	0	0
T5	11190	0	0	0
T6	16786	0	0	0
T22	0	1	0	0
T26	0	6	0	0
T28	4241	0	0	0
T29	4064	5	0	0
T30	3889	0	0	0
T31	2567	0	0	0
T32	3107	5	0	0
T33	4275	0	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	0	2	0	0
T71	0	4	0	0
T93	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	81698752	2195	0	0
TransStop_A	81698752	1129	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698752	2195	0	0
T1	99885	0	0	0
T4	2387	1	0	0
T5	11190	0	0	0
T6	16786	0	0	0
T22	0	1	0	0
T26	0	6	0	0
T28	4241	0	0	0
T29	4064	6	0	0
T30	3889	0	0	0
T31	2567	0	0	0
T32	3107	6	0	0
T33	4275	0	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	0	7	0	0
T71	0	8	0	0
T93	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698752	1129	0	0
T1	99885	0	0	0
T4	2387	1	0	0
T5	11190	0	0	0
T6	16786	0	0	0
T22	0	1	0	0
T26	0	3	0	0
T28	4241	0	0	0
T29	4064	4	0	0
T30	3889	0	0	0
T31	2567	0	0	0
T32	3107	3	0	0
T33	4275	0	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	0	3	0	0
T71	0	2	0	0
T93	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	81698752	2188	0	0
TransStop_A	81698752	1162	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698752	2188	0	0
T1	99885	0	0	0
T4	2387	1	0	0
T5	11190	0	0	0
T6	16786	0	0	0
T22	0	1	0	0
T26	0	7	0	0
T28	4241	0	0	0
T29	4064	5	0	0
T30	3889	0	0	0
T31	2567	0	0	0
T32	3107	6	0	0
T33	4275	0	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	0	11	0	0
T71	0	8	0	0
T93	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698752	1162	0	0
T1	99885	0	0	0
T4	2387	1	0	0
T5	11190	0	0	0
T6	16786	0	0	0
T22	0	1	0	0
T26	0	4	0	0
T28	4241	0	0	0
T29	4064	3	0	0
T30	3889	0	0	0
T31	2567	0	0	0
T32	3107	2	0	0
T33	4275	0	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	0	4	0	0
T71	0	3	0	0
T93	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	81698752	2261	0	0
TransStop_A	81698752	1159	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698752	2261	0	0
T1	99885	0	0	0
T4	2387	1	0	0
T5	11190	0	0	0
T6	16786	0	0	0
T22	0	1	0	0
T26	0	4	0	0
T28	4241	0	0	0
T29	4064	5	0	0
T30	3889	0	0	0
T31	2567	0	0	0
T32	3107	9	0	0
T33	4275	0	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	0	8	0	0
T71	0	8	0	0
T93	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698752	1159	0	0
T1	99885	0	0	0
T4	2387	1	0	0
T5	11190	0	0	0
T6	16786	0	0	0
T22	0	1	0	0
T26	0	3	0	0
T28	4241	0	0	0
T29	4064	2	0	0
T30	3889	0	0	0
T31	2567	0	0	0
T32	3107	4	0	0
T33	4275	0	0	0
T47	0	1	0	0
T53	0	1	0	0
T57	0	3	0	0
T71	0	3	0	0
T93	0	3	0	0