Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	39433932	497197	0	0
clk_enables_rd_A	39433932	6319	0	0
clk_hints_rd_A	39433932	5558	0	0
extclk_ctrl_rd_A	39433932	8777	0	0
extclk_ctrl_regwen_rd_A	39433932	4766	0	0
jitter_enable_rd_A	39433932	10842	0	0
jitter_regwen_rd_A	39433932	4715	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39433932	497197	0	0
T14	38653	0	0	0
T15	0	5870	0	0
T38	142783	6891	0	0
T40	0	5522	0	0
T59	0	8285	0	0
T60	0	9447	0	0
T66	0	7346	0	0
T81	0	13901	0	0
T82	0	9936	0	0
T83	0	4262	0	0
T84	0	5432	0	0
T85	895	0	0	0
T86	3322	0	0	0
T87	1572	0	0	0
T88	138522	0	0	0
T89	1924	0	0	0
T90	907	0	0	0
T91	1477	0	0	0
T92	1181	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39433932	6319	0	0
T1	27970	0	0	0
T4	2386	3	0	0
T5	2461	0	0	0
T6	838	0	0	0
T16	0	7	0	0
T28	1164	0	0	0
T29	2031	0	0	0
T30	1867	0	0	0
T31	2566	0	0	0
T32	2982	0	0	0
T33	1068	0	0	0
T50	0	3	0	0
T59	0	402	0	0
T155	0	1	0	0
T156	0	7	0	0
T157	0	2	0	0
T158	0	5	0	0
T159	0	4	0	0
T160	0	9	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39433932	5558	0	0
T1	27970	0	0	0
T4	2386	2	0	0
T5	2461	0	0	0
T6	838	0	0	0
T16	0	4	0	0
T28	1164	0	0	0
T29	2031	0	0	0
T30	1867	0	0	0
T31	2566	0	0	0
T32	2982	0	0	0
T33	1068	0	0	0
T50	0	4	0	0
T59	0	261	0	0
T155	0	5	0	0
T156	0	2	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	8	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39433932	8777	0	0
T1	27970	0	0	0
T5	2461	75	0	0
T6	838	0	0	0
T23	0	51	0	0
T28	1164	0	0	0
T29	2031	0	0	0
T30	1867	0	0	0
T31	2566	0	0	0
T32	2982	0	0	0
T33	1068	6	0	0
T43	0	23	0	0
T50	0	36	0	0
T51	2327	68	0	0
T70	0	12	0	0
T72	0	11	0	0
T94	0	29	0	0
T162	0	5	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39433932	4766	0	0
T37	65626	0	0	0
T59	0	284	0	0
T68	18720	0	0	0
T94	77095	21	0	0
T96	0	9	0	0
T162	876	0	0	0
T163	0	10	0	0
T164	0	27	0	0
T165	0	313	0	0
T166	0	236	0	0
T167	0	143	0	0
T168	0	205	0	0
T169	0	11	0	0
T170	1935	0	0	0
T171	874	0	0	0
T172	1594	0	0	0
T173	1470	0	0	0
T174	1752	0	0	0
T175	1101	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39433932	10842	0	0
T1	27970	0	0	0
T4	2386	154	0	0
T5	2461	0	0	0
T6	838	0	0	0
T16	0	152	0	0
T28	1164	0	0	0
T29	2031	0	0	0
T30	1867	0	0	0
T31	2566	0	0	0
T32	2982	0	0	0
T33	1068	0	0	0
T50	0	128	0	0
T59	0	762	0	0
T155	0	144	0	0
T156	0	110	0	0
T157	0	53	0	0
T158	0	113	0	0
T159	0	79	0	0
T160	0	240	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39433932	4715	0	0
T59	288814	342	0	0
T60	268267	0	0	0
T129	0	7	0	0
T165	0	383	0	0
T166	0	264	0	0
T167	0	192	0	0
T168	0	234	0	0
T176	0	312	0	0
T177	0	62	0	0
T178	0	706	0	0
T179	0	369	0	0
T180	44316	0	0	0
T181	828	0	0	0
T182	28663	0	0	0
T183	1675	0	0	0
T184	1089	0	0	0
T185	2181	0	0	0
T186	3027	0	0	0
T187	409386	0	0	0