Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	115668738	473	0	0
StatusRise_A	115668738	473	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115668738	473	0	0
T1	83910	0	0	0
T25	0	13	0	0
T28	3492	15	0	0
T29	6093	0	0	0
T30	5601	0	0	0
T31	7698	0	0	0
T32	8946	0	0	0
T33	3204	0	0	0
T51	6981	0	0	0
T52	3897	0	0	0
T53	4608	0	0	0
T61	0	12	0	0
T87	0	11	0	0
T115	0	2	0	0
T188	0	12	0	0
T189	0	14	0	0
T190	0	8	0	0
T191	0	10	0	0
T192	0	14	0	0
T193	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115668738	473	0	0
T1	83910	0	0	0
T25	0	13	0	0
T28	3492	15	0	0
T29	6093	0	0	0
T30	5601	0	0	0
T31	7698	0	0	0
T32	8946	0	0	0
T33	3204	0	0	0
T51	6981	0	0	0
T52	3897	0	0	0
T53	4608	0	0	0
T61	0	12	0	0
T87	0	11	0	0
T115	0	2	0	0
T188	0	12	0	0
T189	0	14	0	0
T190	0	8	0	0
T191	0	10	0	0
T192	0	14	0	0
T193	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38556246	152	0	0
StatusRise_A	38556246	152	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	152	0	0
T1	27970	0	0	0
T25	0	4	0	0
T28	1164	4	0	0
T29	2031	0	0	0
T30	1867	0	0	0
T31	2566	0	0	0
T32	2982	0	0	0
T33	1068	0	0	0
T51	2327	0	0	0
T52	1299	0	0	0
T53	1536	0	0	0
T61	0	4	0	0
T87	0	3	0	0
T115	0	1	0	0
T188	0	3	0	0
T189	0	3	0	0
T190	0	3	0	0
T191	0	3	0	0
T192	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	152	0	0
T1	27970	0	0	0
T25	0	4	0	0
T28	1164	4	0	0
T29	2031	0	0	0
T30	1867	0	0	0
T31	2566	0	0	0
T32	2982	0	0	0
T33	1068	0	0	0
T51	2327	0	0	0
T52	1299	0	0	0
T53	1536	0	0	0
T61	0	4	0	0
T87	0	3	0	0
T115	0	1	0	0
T188	0	3	0	0
T189	0	3	0	0
T190	0	3	0	0
T191	0	3	0	0
T192	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38556246	159	0	0
StatusRise_A	38556246	159	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	159	0	0
T1	27970	0	0	0
T25	0	5	0	0
T28	1164	5	0	0
T29	2031	0	0	0
T30	1867	0	0	0
T31	2566	0	0	0
T32	2982	0	0	0
T33	1068	0	0	0
T51	2327	0	0	0
T52	1299	0	0	0
T53	1536	0	0	0
T61	0	3	0	0
T87	0	4	0	0
T188	0	4	0	0
T189	0	4	0	0
T190	0	2	0	0
T191	0	4	0	0
T192	0	3	0	0
T193	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	159	0	0
T1	27970	0	0	0
T25	0	5	0	0
T28	1164	5	0	0
T29	2031	0	0	0
T30	1867	0	0	0
T31	2566	0	0	0
T32	2982	0	0	0
T33	1068	0	0	0
T51	2327	0	0	0
T52	1299	0	0	0
T53	1536	0	0	0
T61	0	3	0	0
T87	0	4	0	0
T188	0	4	0	0
T189	0	4	0	0
T190	0	2	0	0
T191	0	4	0	0
T192	0	3	0	0
T193	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38556246	162	0	0
StatusRise_A	38556246	162	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	162	0	0
T1	27970	0	0	0
T25	0	4	0	0
T28	1164	6	0	0
T29	2031	0	0	0
T30	1867	0	0	0
T31	2566	0	0	0
T32	2982	0	0	0
T33	1068	0	0	0
T51	2327	0	0	0
T52	1299	0	0	0
T53	1536	0	0	0
T61	0	5	0	0
T87	0	4	0	0
T115	0	1	0	0
T188	0	5	0	0
T189	0	7	0	0
T190	0	3	0	0
T191	0	3	0	0
T192	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38556246	162	0	0
T1	27970	0	0	0
T25	0	4	0	0
T28	1164	6	0	0
T29	2031	0	0	0
T30	1867	0	0	0
T31	2566	0	0	0
T32	2982	0	0	0
T33	1068	0	0	0
T51	2327	0	0	0
T52	1299	0	0	0
T53	1536	0	0	0
T61	0	5	0	0
T87	0	4	0	0
T115	0	1	0	0
T188	0	5	0	0
T189	0	7	0	0
T190	0	3	0	0
T191	0	3	0	0
T192	0	6	0	0