Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T2
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	858676904	30974	0	0
CgEnOn_A	858676904	21807	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	858676904	30974	0	0
T1	1078558	3	0	0
T4	14668	7	0	0
T5	70029	3	0	0
T6	103356	27	0	0
T25	0	29	0	0
T28	46564	47	0	0
T29	43728	13	0	0
T30	42192	3	0	0
T31	27898	3	0	0
T32	33420	10	0	0
T33	46454	3	0	0
T51	45269	0	0	0
T52	6024	0	0	0
T53	7548	1	0	0
T57	0	6	0	0
T61	0	19	0	0
T87	0	20	0	0
T188	0	20	0	0
T189	0	20	0	0
T190	0	10	0	0
T191	0	20	0	0
T192	0	15	0	0
T193	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	858676904	21807	0	0
T1	1078558	0	0	0
T4	14668	4	0	0
T5	70029	0	0	0
T6	103356	24	0	0
T22	0	4	0	0
T24	0	34	0	0
T25	0	44	0	0
T28	46564	44	0	0
T29	43728	10	0	0
T30	42192	0	0	0
T31	27898	0	0	0
T32	33420	7	0	0
T33	46454	0	0	0
T47	0	3	0	0
T51	45269	0	0	0
T52	6024	0	0	0
T53	7548	3	0	0
T56	0	42	0	0
T57	0	6	0	0
T61	0	28	0	0
T87	0	20	0	0
T188	0	20	0	0
T189	0	20	0	0
T190	0	10	0	0
T191	0	20	0	0
T192	0	15	0	0
T193	0	15	0	0
T194	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	35897717	178	0	0
CgEnOn_A	35897717	178	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35897717	178	0	0
T1	47897	0	0	0
T25	0	5	0	0
T28	2112	5	0	0
T29	1911	0	0	0
T30	1916	0	0	0
T31	1280	0	0	0
T32	1458	0	0	0
T33	2126	0	0	0
T51	5298	0	0	0
T52	622	0	0	0
T53	772	0	0	0
T61	0	3	0	0
T87	0	4	0	0
T188	0	4	0	0
T189	0	4	0	0
T190	0	2	0	0
T191	0	4	0	0
T192	0	3	0	0
T193	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35897717	178	0	0
T1	47897	0	0	0
T25	0	5	0	0
T28	2112	5	0	0
T29	1911	0	0	0
T30	1916	0	0	0
T31	1280	0	0	0
T32	1458	0	0	0
T33	2126	0	0	0
T51	5298	0	0	0
T52	622	0	0	0
T53	772	0	0	0
T61	0	3	0	0
T87	0	4	0	0
T188	0	4	0	0
T189	0	4	0	0
T190	0	2	0	0
T191	0	4	0	0
T192	0	3	0	0
T193	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	17948391	178	0	0
CgEnOn_A	17948391	178	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17948391	178	0	0
T1	23948	0	0	0
T25	0	5	0	0
T28	1056	5	0	0
T29	955	0	0	0
T30	958	0	0	0
T31	638	0	0	0
T32	729	0	0	0
T33	1062	0	0	0
T51	2647	0	0	0
T52	311	0	0	0
T53	386	0	0	0
T61	0	3	0	0
T87	0	4	0	0
T188	0	4	0	0
T189	0	4	0	0
T190	0	2	0	0
T191	0	4	0	0
T192	0	3	0	0
T193	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17948391	178	0	0
T1	23948	0	0	0
T25	0	5	0	0
T28	1056	5	0	0
T29	955	0	0	0
T30	958	0	0	0
T31	638	0	0	0
T32	729	0	0	0
T33	1062	0	0	0
T51	2647	0	0	0
T52	311	0	0	0
T53	386	0	0	0
T61	0	3	0	0
T87	0	4	0	0
T188	0	4	0	0
T189	0	4	0	0
T190	0	2	0	0
T191	0	4	0	0
T192	0	3	0	0
T193	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	17948391	178	0	0
CgEnOn_A	17948391	178	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17948391	178	0	0
T1	23948	0	0	0
T25	0	5	0	0
T28	1056	5	0	0
T29	955	0	0	0
T30	958	0	0	0
T31	638	0	0	0
T32	729	0	0	0
T33	1062	0	0	0
T51	2647	0	0	0
T52	311	0	0	0
T53	386	0	0	0
T61	0	3	0	0
T87	0	4	0	0
T188	0	4	0	0
T189	0	4	0	0
T190	0	2	0	0
T191	0	4	0	0
T192	0	3	0	0
T193	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17948391	178	0	0
T1	23948	0	0	0
T25	0	5	0	0
T28	1056	5	0	0
T29	955	0	0	0
T30	958	0	0	0
T31	638	0	0	0
T32	729	0	0	0
T33	1062	0	0	0
T51	2647	0	0	0
T52	311	0	0	0
T53	386	0	0	0
T61	0	3	0	0
T87	0	4	0	0
T188	0	4	0	0
T189	0	4	0	0
T190	0	2	0	0
T191	0	4	0	0
T192	0	3	0	0
T193	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	17948391	178	0	0
CgEnOn_A	17948391	178	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17948391	178	0	0
T1	23948	0	0	0
T25	0	5	0	0
T28	1056	5	0	0
T29	955	0	0	0
T30	958	0	0	0
T31	638	0	0	0
T32	729	0	0	0
T33	1062	0	0	0
T51	2647	0	0	0
T52	311	0	0	0
T53	386	0	0	0
T61	0	3	0	0
T87	0	4	0	0
T188	0	4	0	0
T189	0	4	0	0
T190	0	2	0	0
T191	0	4	0	0
T192	0	3	0	0
T193	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17948391	178	0	0
T1	23948	0	0	0
T25	0	5	0	0
T28	1056	5	0	0
T29	955	0	0	0
T30	958	0	0	0
T31	638	0	0	0
T32	729	0	0	0
T33	1062	0	0	0
T51	2647	0	0	0
T52	311	0	0	0
T53	386	0	0	0
T61	0	3	0	0
T87	0	4	0	0
T188	0	4	0	0
T189	0	4	0	0
T190	0	2	0	0
T191	0	4	0	0
T192	0	3	0	0
T193	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	73311726	178	0	0
CgEnOn_A	73311726	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73311726	178	0	0
T1	95886	0	0	0
T25	0	5	0	0
T28	4248	5	0	0
T29	3901	0	0	0
T30	3733	0	0	0
T31	2464	0	0	0
T32	2982	0	0	0
T33	4103	0	0	0
T51	8939	0	0	0
T52	1247	0	0	0
T53	1568	0	0	0
T61	0	3	0	0
T87	0	4	0	0
T188	0	4	0	0
T189	0	4	0	0
T190	0	2	0	0
T191	0	4	0	0
T192	0	3	0	0
T193	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73311726	163	0	0
T1	95886	0	0	0
T25	0	5	0	0
T28	4248	5	0	0
T29	3901	0	0	0
T30	3733	0	0	0
T31	2464	0	0	0
T32	2982	0	0	0
T33	4103	0	0	0
T51	8939	0	0	0
T52	1247	0	0	0
T53	1568	0	0	0
T61	0	3	0	0
T87	0	4	0	0
T188	0	4	0	0
T189	0	4	0	0
T190	0	2	0	0
T191	0	4	0	0
T192	0	3	0	0
T193	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81698299	155	0	0
CgEnOn_A	81698299	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698299	155	0	0
T1	99885	0	0	0
T25	0	4	0	0
T28	4240	4	0	0
T29	4064	0	0	0
T30	3888	0	0	0
T31	2566	0	0	0
T32	3107	0	0	0
T33	4274	0	0	0
T51	9311	0	0	0
T52	1299	0	0	0
T53	1633	0	0	0
T61	0	4	0	0
T87	0	3	0	0
T115	0	1	0	0
T188	0	3	0	0
T189	0	3	0	0
T190	0	3	0	0
T191	0	3	0	0
T192	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698299	153	0	0
T1	99885	0	0	0
T25	0	4	0	0
T28	4240	4	0	0
T29	4064	0	0	0
T30	3888	0	0	0
T31	2566	0	0	0
T32	3107	0	0	0
T33	4274	0	0	0
T51	9311	0	0	0
T52	1299	0	0	0
T53	1633	0	0	0
T61	0	4	0	0
T87	0	3	0	0
T115	0	1	0	0
T188	0	3	0	0
T189	0	3	0	0
T190	0	3	0	0
T191	0	3	0	0
T192	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81698299	155	0	0
CgEnOn_A	81698299	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698299	155	0	0
T1	99885	0	0	0
T25	0	4	0	0
T28	4240	4	0	0
T29	4064	0	0	0
T30	3888	0	0	0
T31	2566	0	0	0
T32	3107	0	0	0
T33	4274	0	0	0
T51	9311	0	0	0
T52	1299	0	0	0
T53	1633	0	0	0
T61	0	4	0	0
T87	0	3	0	0
T115	0	1	0	0
T188	0	3	0	0
T189	0	3	0	0
T190	0	3	0	0
T191	0	3	0	0
T192	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698299	153	0	0
T1	99885	0	0	0
T25	0	4	0	0
T28	4240	4	0	0
T29	4064	0	0	0
T30	3888	0	0	0
T31	2566	0	0	0
T32	3107	0	0	0
T33	4274	0	0	0
T51	9311	0	0	0
T52	1299	0	0	0
T53	1633	0	0	0
T61	0	4	0	0
T87	0	3	0	0
T115	0	1	0	0
T188	0	3	0	0
T189	0	3	0	0
T190	0	3	0	0
T191	0	3	0	0
T192	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T2
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	39137330	168	0	0
CgEnOn_A	39137330	162	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39137330	168	0	0
T1	47945	0	0	0
T25	0	4	0	0
T28	2090	6	0	0
T29	1950	0	0	0
T30	1867	0	0	0
T31	1231	0	0	0
T32	1491	0	0	0
T33	2052	0	0	0
T51	4469	0	0	0
T52	624	0	0	0
T53	784	0	0	0
T61	0	5	0	0
T66	0	1	0	0
T87	0	4	0	0
T115	0	1	0	0
T188	0	5	0	0
T189	0	7	0	0
T190	0	3	0	0
T191	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39137330	162	0	0
T1	47945	0	0	0
T25	0	4	0	0
T28	2090	6	0	0
T29	1950	0	0	0
T30	1867	0	0	0
T31	1231	0	0	0
T32	1491	0	0	0
T33	2052	0	0	0
T51	4469	0	0	0
T52	624	0	0	0
T53	784	0	0	0
T61	0	5	0	0
T87	0	4	0	0
T115	0	1	0	0
T188	0	5	0	0
T189	0	7	0	0
T190	0	3	0	0
T191	0	3	0	0
T192	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T61,T25
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	17948391	5006	0	0
CgEnOn_A	17948391	2731	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17948391	5006	0	0
T1	23948	1	0	0
T4	563	2	0	0
T5	3052	1	0	0
T6	4015	8	0	0
T28	1056	6	0	0
T29	955	1	0	0
T30	958	1	0	0
T31	638	1	0	0
T32	729	1	0	0
T33	1062	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17948391	2731	0	0
T1	23948	0	0	0
T4	563	1	0	0
T5	3052	0	0	0
T6	4015	7	0	0
T22	0	1	0	0
T24	0	11	0	0
T25	0	5	0	0
T28	1056	5	0	0
T29	955	0	0	0
T30	958	0	0	0
T31	638	0	0	0
T32	729	0	0	0
T33	1062	0	0	0
T47	0	1	0	0
T56	0	14	0	0
T61	0	3	0	0
T194	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T61,T25
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	35897717	5032	0	0
CgEnOn_A	35897717	2757	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35897717	5032	0	0
T1	47897	1	0	0
T4	1126	2	0	0
T5	6106	1	0	0
T6	8031	10	0	0
T28	2112	6	0	0
T29	1911	1	0	0
T30	1916	1	0	0
T31	1280	1	0	0
T32	1458	1	0	0
T33	2126	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35897717	2757	0	0
T1	47897	0	0	0
T4	1126	1	0	0
T5	6106	0	0	0
T6	8031	9	0	0
T22	0	1	0	0
T24	0	12	0	0
T25	0	5	0	0
T28	2112	5	0	0
T29	1911	0	0	0
T30	1916	0	0	0
T31	1280	0	0	0
T32	1458	0	0	0
T33	2126	0	0	0
T47	0	1	0	0
T53	0	1	0	0
T56	0	13	0	0
T61	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T61,T25
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	73311726	5044	0	0
CgEnOn_A	73311726	2754	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73311726	5044	0	0
T1	95886	1	0	0
T4	2290	2	0	0
T5	10741	1	0	0
T6	16113	9	0	0
T28	4248	6	0	0
T29	3901	1	0	0
T30	3733	1	0	0
T31	2464	1	0	0
T32	2982	1	0	0
T33	4103	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73311726	2754	0	0
T1	95886	0	0	0
T4	2290	1	0	0
T5	10741	0	0	0
T6	16113	8	0	0
T22	0	1	0	0
T24	0	11	0	0
T25	0	5	0	0
T28	4248	5	0	0
T29	3901	0	0	0
T30	3733	0	0	0
T31	2464	0	0	0
T32	2982	0	0	0
T33	4103	0	0	0
T47	0	1	0	0
T53	0	1	0	0
T56	0	15	0	0
T61	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T61,T25
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	39137330	5059	0	0
CgEnOn_A	39137330	2765	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39137330	5059	0	0
T1	47945	1	0	0
T4	1145	2	0	0
T5	5370	1	0	0
T6	8057	9	0	0
T28	2090	7	0	0
T29	1950	1	0	0
T30	1867	1	0	0
T31	1231	1	0	0
T32	1491	1	0	0
T33	2052	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39137330	2765	0	0
T1	47945	0	0	0
T4	1145	1	0	0
T5	5370	0	0	0
T6	8057	8	0	0
T22	0	1	0	0
T24	0	12	0	0
T25	0	4	0	0
T28	2090	6	0	0
T29	1950	0	0	0
T30	1867	0	0	0
T31	1231	0	0	0
T32	1491	0	0	0
T33	2052	0	0	0
T47	0	1	0	0
T53	0	1	0	0
T56	0	14	0	0
T61	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T2
1	0	Covered	T4,T29,T32
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81698299	2356	0	0
CgEnOn_A	81698299	2354	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698299	2356	0	0
T1	99885	0	0	0
T4	2386	1	0	0
T5	11190	0	0	0
T6	16785	0	0	0
T22	0	1	0	0
T25	0	4	0	0
T28	4240	4	0	0
T29	4064	10	0	0
T30	3888	0	0	0
T31	2566	0	0	0
T32	3107	7	0	0
T33	4274	0	0	0
T53	0	1	0	0
T57	0	6	0	0
T61	0	4	0	0
T71	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698299	2354	0	0
T1	99885	0	0	0
T4	2386	1	0	0
T5	11190	0	0	0
T6	16785	0	0	0
T22	0	1	0	0
T25	0	4	0	0
T28	4240	4	0	0
T29	4064	10	0	0
T30	3888	0	0	0
T31	2566	0	0	0
T32	3107	7	0	0
T33	4274	0	0	0
T53	0	1	0	0
T57	0	6	0	0
T61	0	4	0	0
T71	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T2
1	0	Covered	T4,T29,T32
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81698299	2350	0	0
CgEnOn_A	81698299	2348	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698299	2350	0	0
T1	99885	0	0	0
T4	2386	1	0	0
T5	11190	0	0	0
T6	16785	0	0	0
T22	0	1	0	0
T25	0	4	0	0
T28	4240	4	0	0
T29	4064	6	0	0
T30	3888	0	0	0
T31	2566	0	0	0
T32	3107	6	0	0
T33	4274	0	0	0
T53	0	1	0	0
T57	0	7	0	0
T61	0	4	0	0
T71	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698299	2348	0	0
T1	99885	0	0	0
T4	2386	1	0	0
T5	11190	0	0	0
T6	16785	0	0	0
T22	0	1	0	0
T25	0	4	0	0
T28	4240	4	0	0
T29	4064	6	0	0
T30	3888	0	0	0
T31	2566	0	0	0
T32	3107	6	0	0
T33	4274	0	0	0
T53	0	1	0	0
T57	0	7	0	0
T61	0	4	0	0
T71	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T2
1	0	Covered	T4,T29,T32
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81698299	2343	0	0
CgEnOn_A	81698299	2341	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698299	2343	0	0
T1	99885	0	0	0
T4	2386	1	0	0
T5	11190	0	0	0
T6	16785	0	0	0
T22	0	1	0	0
T25	0	4	0	0
T28	4240	4	0	0
T29	4064	5	0	0
T30	3888	0	0	0
T31	2566	0	0	0
T32	3107	6	0	0
T33	4274	0	0	0
T53	0	1	0	0
T57	0	11	0	0
T61	0	4	0	0
T71	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698299	2341	0	0
T1	99885	0	0	0
T4	2386	1	0	0
T5	11190	0	0	0
T6	16785	0	0	0
T22	0	1	0	0
T25	0	4	0	0
T28	4240	4	0	0
T29	4064	5	0	0
T30	3888	0	0	0
T31	2566	0	0	0
T32	3107	6	0	0
T33	4274	0	0	0
T53	0	1	0	0
T57	0	11	0	0
T61	0	4	0	0
T71	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T2
1	0	Covered	T4,T29,T32
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	81698299	2416	0	0
CgEnOn_A	81698299	2414	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698299	2416	0	0
T1	99885	0	0	0
T4	2386	1	0	0
T5	11190	0	0	0
T6	16785	0	0	0
T22	0	1	0	0
T25	0	4	0	0
T28	4240	4	0	0
T29	4064	5	0	0
T30	3888	0	0	0
T31	2566	0	0	0
T32	3107	9	0	0
T33	4274	0	0	0
T53	0	1	0	0
T57	0	8	0	0
T61	0	4	0	0
T71	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	81698299	2414	0	0
T1	99885	0	0	0
T4	2386	1	0	0
T5	11190	0	0	0
T6	16785	0	0	0
T22	0	1	0	0
T25	0	4	0	0
T28	4240	4	0	0
T29	4064	5	0	0
T30	3888	0	0	0
T31	2566	0	0	0
T32	3107	9	0	0
T33	4274	0	0	0
T53	0	1	0	0
T57	0	8	0	0
T61	0	4	0	0
T71	0	8	0	0