Unified Coverage Report :: Module :: clkmgr_clk_status

Module : clkmgr_clk_status

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_0.1/rtl/clkmgr_clk_status.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_main_status	100.00	100.00				100.00
tb.dut.u_io_status	100.00	100.00				100.00
tb.dut.u_usb_status	100.00	100.00				100.00

---

Module Instance : tb.dut.u_main_status

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_en_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_status

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_en_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_usb_status

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_en_sync	100.00	100.00				100.00

Line Coverage for Module : clkmgr_clk_status

	Line No.	Total	Covered	Percent
TOTAL		13	13	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
ALWAYS	39	5	5	100.00
ALWAYS	49	6	6	100.00

32                        // enable is true when all inputs are 1
33         1/1            assign en_d = {en_q[FilterStages-2:0], &ens_sync};
           Tests:       T4 T5 T6 
34                      
35                        // disable is true all all inputs are 0
36         1/1            assign dis_d = {dis_q[FilterStages-2:0], ~|ens_sync};
           Tests:       T4 T5 T6 
37                      
38                        always_ff @(posedge clk_i or negedge rst_ni) begin
39         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
40         1/1                en_q <= '0;
           Tests:       T4 T5 T6 
41         1/1                dis_q <= '0;
           Tests:       T4 T5 T6 
42                          end else begin
43         1/1                en_q <= en_d;
           Tests:       T4 T5 T6 
44         1/1                dis_q <= dis_d;
           Tests:       T4 T5 T6 
45                          end
46                        end
47                      
48                        always_ff @(posedge clk_i or negedge rst_ni) begin
49         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
50         1/1                status_o <= '0;
           Tests:       T4 T5 T6 
51         1/1              end else if (&en_q) begin
           Tests:       T4 T5 T6 
52         1/1                status_o <= 1'b1;
           Tests:       T4 T5 T6 
53         1/1              end else if (&dis_q) begin
           Tests:       T4 T5 T6 
54         1/1                status_o <= 1'b0;
           Tests:       T4 T5 T6 
55                          end
                        MISSING_ELSE

---

Branch Coverage for Module : clkmgr_clk_status

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	39	2	2	100.00
IF	49	4	4	100.00

39             if (!rst_ni) begin
               -1-  
40               en_q <= '0;
                 ==>
41               dis_q <= '0;
42             end else begin
43               en_q <= en_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

49             if (!rst_ni) begin
               -1-  
50               status_o <= '0;
                 ==>
51             end else if (&en_q) begin
                        -2-  
52               status_o <= 1'b1;
                 ==>
53             end else if (&dis_q) begin
                        -3-  
54               status_o <= 1'b0;
                 ==>
55             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_main_status

	Line No.	Total	Covered	Percent
TOTAL		13	13	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
ALWAYS	39	5	5	100.00
ALWAYS	49	6	6	100.00

32                        // enable is true when all inputs are 1
33         1/1            assign en_d = {en_q[FilterStages-2:0], &ens_sync};
           Tests:       T4 T5 T6 
34                      
35                        // disable is true all all inputs are 0
36         1/1            assign dis_d = {dis_q[FilterStages-2:0], ~|ens_sync};
           Tests:       T4 T5 T6 
37                      
38                        always_ff @(posedge clk_i or negedge rst_ni) begin
39         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
40         1/1                en_q <= '0;
           Tests:       T4 T5 T6 
41         1/1                dis_q <= '0;
           Tests:       T4 T5 T6 
42                          end else begin
43         1/1                en_q <= en_d;
           Tests:       T4 T5 T6 
44         1/1                dis_q <= dis_d;
           Tests:       T4 T5 T6 
45                          end
46                        end
47                      
48                        always_ff @(posedge clk_i or negedge rst_ni) begin
49         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
50         1/1                status_o <= '0;
           Tests:       T4 T5 T6 
51         1/1              end else if (&en_q) begin
           Tests:       T4 T5 T6 
52         1/1                status_o <= 1'b1;
           Tests:       T4 T5 T6 
53         1/1              end else if (&dis_q) begin
           Tests:       T4 T5 T6 
54         1/1                status_o <= 1'b0;
           Tests:       T4 T5 T6 
55                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_main_status

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	39	2	2	100.00
IF	49	4	4	100.00

39             if (!rst_ni) begin
               -1-  
40               en_q <= '0;
                 ==>
41               dis_q <= '0;
42             end else begin
43               en_q <= en_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

49             if (!rst_ni) begin
               -1-  
50               status_o <= '0;
                 ==>
51             end else if (&en_q) begin
                        -2-  
52               status_o <= 1'b1;
                 ==>
53             end else if (&dis_q) begin
                        -3-  
54               status_o <= 1'b0;
                 ==>
55             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_io_status

	Line No.	Total	Covered	Percent
TOTAL		13	13	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
ALWAYS	39	5	5	100.00
ALWAYS	49	6	6	100.00

32                        // enable is true when all inputs are 1
33         1/1            assign en_d = {en_q[FilterStages-2:0], &ens_sync};
           Tests:       T4 T5 T6 
34                      
35                        // disable is true all all inputs are 0
36         1/1            assign dis_d = {dis_q[FilterStages-2:0], ~|ens_sync};
           Tests:       T4 T5 T6 
37                      
38                        always_ff @(posedge clk_i or negedge rst_ni) begin
39         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
40         1/1                en_q <= '0;
           Tests:       T4 T5 T6 
41         1/1                dis_q <= '0;
           Tests:       T4 T5 T6 
42                          end else begin
43         1/1                en_q <= en_d;
           Tests:       T4 T5 T6 
44         1/1                dis_q <= dis_d;
           Tests:       T4 T5 T6 
45                          end
46                        end
47                      
48                        always_ff @(posedge clk_i or negedge rst_ni) begin
49         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
50         1/1                status_o <= '0;
           Tests:       T4 T5 T6 
51         1/1              end else if (&en_q) begin
           Tests:       T4 T5 T6 
52         1/1                status_o <= 1'b1;
           Tests:       T4 T5 T6 
53         1/1              end else if (&dis_q) begin
           Tests:       T4 T5 T6 
54         1/1                status_o <= 1'b0;
           Tests:       T4 T5 T6 
55                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_io_status

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	39	2	2	100.00
IF	49	4	4	100.00

39             if (!rst_ni) begin
               -1-  
40               en_q <= '0;
                 ==>
41               dis_q <= '0;
42             end else begin
43               en_q <= en_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

49             if (!rst_ni) begin
               -1-  
50               status_o <= '0;
                 ==>
51             end else if (&en_q) begin
                        -2-  
52               status_o <= 1'b1;
                 ==>
53             end else if (&dis_q) begin
                        -3-  
54               status_o <= 1'b0;
                 ==>
55             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_usb_status

	Line No.	Total	Covered	Percent
TOTAL		13	13	100.00
CONT_ASSIGN	33	1	1	100.00
CONT_ASSIGN	36	1	1	100.00
ALWAYS	39	5	5	100.00
ALWAYS	49	6	6	100.00

32                        // enable is true when all inputs are 1
33         1/1            assign en_d = {en_q[FilterStages-2:0], &ens_sync};
           Tests:       T4 T5 T6 
34                      
35                        // disable is true all all inputs are 0
36         1/1            assign dis_d = {dis_q[FilterStages-2:0], ~|ens_sync};
           Tests:       T4 T5 T6 
37                      
38                        always_ff @(posedge clk_i or negedge rst_ni) begin
39         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
40         1/1                en_q <= '0;
           Tests:       T4 T5 T6 
41         1/1                dis_q <= '0;
           Tests:       T4 T5 T6 
42                          end else begin
43         1/1                en_q <= en_d;
           Tests:       T4 T5 T6 
44         1/1                dis_q <= dis_d;
           Tests:       T4 T5 T6 
45                          end
46                        end
47                      
48                        always_ff @(posedge clk_i or negedge rst_ni) begin
49         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
50         1/1                status_o <= '0;
           Tests:       T4 T5 T6 
51         1/1              end else if (&en_q) begin
           Tests:       T4 T5 T6 
52         1/1                status_o <= 1'b1;
           Tests:       T4 T5 T6 
53         1/1              end else if (&dis_q) begin
           Tests:       T4 T5 T6 
54         1/1                status_o <= 1'b0;
           Tests:       T4 T5 T6 
55                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_usb_status

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	39	2	2	100.00
IF	49	4	4	100.00

39             if (!rst_ni) begin
               -1-  
40               en_q <= '0;
                 ==>
41               dis_q <= '0;
42             end else begin
43               en_q <= en_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

49             if (!rst_ni) begin
               -1-  
50               status_o <= '0;
                 ==>
51             end else if (&en_q) begin
                        -2-  
52               status_o <= 1'b1;
                 ==>
53             end else if (&dis_q) begin
                        -3-  
54               status_o <= 1'b0;
                 ==>
55             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T4,T5,T6