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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 1010
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T1001 /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/40.clkmgr_intr_test.190928111 Aug 23 06:03:41 AM UTC 24 Aug 23 06:03:42 AM UTC 24 20025957 ps
T1002 /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/41.clkmgr_intr_test.1520619860 Aug 23 06:03:42 AM UTC 24 Aug 23 06:03:44 AM UTC 24 24969874 ps
T1003 /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/45.clkmgr_intr_test.538939651 Aug 23 06:03:42 AM UTC 24 Aug 23 06:03:44 AM UTC 24 13335802 ps
T1004 /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/46.clkmgr_intr_test.2880319326 Aug 23 06:03:42 AM UTC 24 Aug 23 06:03:44 AM UTC 24 12839875 ps
T1005 /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/43.clkmgr_intr_test.3139977084 Aug 23 06:03:42 AM UTC 24 Aug 23 06:03:44 AM UTC 24 14162096 ps
T1006 /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/42.clkmgr_intr_test.995349061 Aug 23 06:03:42 AM UTC 24 Aug 23 06:03:44 AM UTC 24 26362065 ps
T1007 /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/44.clkmgr_intr_test.2651899578 Aug 23 06:03:42 AM UTC 24 Aug 23 06:03:44 AM UTC 24 36662599 ps
T1008 /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/47.clkmgr_intr_test.3629037690 Aug 23 06:03:42 AM UTC 24 Aug 23 06:03:44 AM UTC 24 15813394 ps
T1009 /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/48.clkmgr_intr_test.4127188351 Aug 23 06:03:42 AM UTC 24 Aug 23 06:03:44 AM UTC 24 25871862 ps
T1010 /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/49.clkmgr_intr_test.1739461019 Aug 23 06:03:42 AM UTC 24 Aug 23 06:03:44 AM UTC 24 19801319 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency_timeout.3377471424
Short name T1
Test name
Test status
Simulation time 1118874890 ps
CPU time 4.8 seconds
Started Aug 23 06:13:26 AM UTC 24
Finished Aug 23 06:13:32 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377471424 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_timeout.3377471424
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.506910218
Short name T51
Test name
Test status
Simulation time 93141935 ps
CPU time 0.99 seconds
Started Aug 23 06:13:30 AM UTC 24
Finished Aug 23 06:13:32 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506910218 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_handshake_intersig_mubi.506910218
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all_with_rand_reset.1382618129
Short name T38
Test name
Test status
Simulation time 1442270554 ps
CPU time 23.51 seconds
Started Aug 23 06:13:44 AM UTC 24
Finished Aug 23 06:14:09 AM UTC 24
Peak memory 227184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382618129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.1382618129
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all.2731654600
Short name T50
Test name
Test status
Simulation time 4710490387 ps
CPU time 17.16 seconds
Started Aug 23 06:13:32 AM UTC 24
Finished Aug 23 06:13:50 AM UTC 24
Peak memory 210484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731654600 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all.2731654600
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency.907634130
Short name T10
Test name
Test status
Simulation time 1883861469 ps
CPU time 14.25 seconds
Started Aug 23 06:13:33 AM UTC 24
Finished Aug 23 06:13:48 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907634130 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.907634130
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.1147260456
Short name T75
Test name
Test status
Simulation time 84212615 ps
CPU time 1.47 seconds
Started Aug 23 06:02:54 AM UTC 24
Finished Aug 23 06:02:56 AM UTC 24
Peak memory 220760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147260
456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors.1147260456
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_smoke.4251307005
Short name T4
Test name
Test status
Simulation time 23887638 ps
CPU time 0.78 seconds
Started Aug 23 06:13:23 AM UTC 24
Finished Aug 23 06:13:25 AM UTC 24
Peak memory 209652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251307005 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.4251307005
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_regwen.712220054
Short name T48
Test name
Test status
Simulation time 1042879364 ps
CPU time 3.81 seconds
Started Aug 23 06:13:43 AM UTC 24
Finished Aug 23 06:13:48 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712220054 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.712220054
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_sec_cm.3530611062
Short name T55
Test name
Test status
Simulation time 330133339 ps
CPU time 2.19 seconds
Started Aug 23 06:13:31 AM UTC 24
Finished Aug 23 06:13:35 AM UTC 24
Peak memory 242336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530611062 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_sec_cm.3530611062
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_status.2442122208
Short name T28
Test name
Test status
Simulation time 48568285 ps
CPU time 0.69 seconds
Started Aug 23 06:13:28 AM UTC 24
Finished Aug 23 06:13:30 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442122208 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.2442122208
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_idle_intersig_mubi.2311546736
Short name T71
Test name
Test status
Simulation time 112703103 ps
CPU time 1.09 seconds
Started Aug 23 06:13:35 AM UTC 24
Finished Aug 23 06:13:37 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311546736 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_idle_intersig_mubi.2311546736
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_intg_err.3515095712
Short name T125
Test name
Test status
Simulation time 219758078 ps
CPU time 2.18 seconds
Started Aug 23 06:02:50 AM UTC 24
Finished Aug 23 06:02:53 AM UTC 24
Peak memory 212216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515095712 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_intg_err.3515095712
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all.3297047901
Short name T16
Test name
Test status
Simulation time 8623945955 ps
CPU time 33.2 seconds
Started Aug 23 06:13:51 AM UTC 24
Finished Aug 23 06:14:26 AM UTC 24
Peak memory 210832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297047901 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all.3297047901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.1573650333
Short name T30
Test name
Test status
Simulation time 38910425 ps
CPU time 0.77 seconds
Started Aug 23 06:13:29 AM UTC 24
Finished Aug 23 06:13:31 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573650333
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_ctrl_intersig_mubi.1573650333
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all_with_rand_reset.2074182926
Short name T200
Test name
Test status
Simulation time 5989960250 ps
CPU time 93.01 seconds
Started Aug 23 06:15:12 AM UTC 24
Finished Aug 23 06:16:47 AM UTC 24
Peak memory 227960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074182926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.2074182926
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_div_intersig_mubi.2043582989
Short name T44
Test name
Test status
Simulation time 232184850 ps
CPU time 1.33 seconds
Started Aug 23 06:13:43 AM UTC 24
Finished Aug 23 06:13:45 AM UTC 24
Peak memory 209676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043582989 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_div_intersig_mubi.2043582989
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_alert_test.2654717517
Short name T54
Test name
Test status
Simulation time 50076130 ps
CPU time 0.78 seconds
Started Aug 23 06:13:33 AM UTC 24
Finished Aug 23 06:13:35 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654717517 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_alert_test.2654717517
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3900772482
Short name T142
Test name
Test status
Simulation time 268493316 ps
CPU time 1.88 seconds
Started Aug 23 06:03:29 AM UTC 24
Finished Aug 23 06:03:32 AM UTC 24
Peak memory 211708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900772
482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors.3900772482
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/11.clkmgr_regwen.1928095185
Short name T163
Test name
Test status
Simulation time 481118728 ps
CPU time 1.94 seconds
Started Aug 23 06:14:45 AM UTC 24
Finished Aug 23 06:14:48 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928095185 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.1928095185
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/20.clkmgr_regwen.1807552487
Short name T7
Test name
Test status
Simulation time 617934103 ps
CPU time 3.45 seconds
Started Aug 23 06:15:32 AM UTC 24
Finished Aug 23 06:15:37 AM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807552487 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.1807552487
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.1791014232
Short name T76
Test name
Test status
Simulation time 147672266 ps
CPU time 2.38 seconds
Started Aug 23 06:02:54 AM UTC 24
Finished Aug 23 06:02:57 AM UTC 24
Peak memory 221988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1791014232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_
errors_with_csr_rw.1791014232
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1167039697
Short name T132
Test name
Test status
Simulation time 82238230 ps
CPU time 1.62 seconds
Started Aug 23 06:03:33 AM UTC 24
Finished Aug 23 06:03:36 AM UTC 24
Peak memory 211880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167039697 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_intg_err.1167039697
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1945869650
Short name T145
Test name
Test status
Simulation time 599417726 ps
CPU time 2.8 seconds
Started Aug 23 06:03:20 AM UTC 24
Finished Aug 23 06:03:24 AM UTC 24
Peak memory 212944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945869
650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors.1945869650
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.2521624510
Short name T129
Test name
Test status
Simulation time 27576224 ps
CPU time 0.78 seconds
Started Aug 23 06:02:51 AM UTC 24
Finished Aug 23 06:02:53 AM UTC 24
Peak memory 212168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521624510 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_hw_reset.2521624510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.2501289100
Short name T118
Test name
Test status
Simulation time 43215046 ps
CPU time 0.76 seconds
Started Aug 23 06:14:38 AM UTC 24
Finished Aug 23 06:14:40 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501289100 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_handshake_intersig_mubi.2501289100
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_intg_err.3038712107
Short name T126
Test name
Test status
Simulation time 98908224 ps
CPU time 2.19 seconds
Started Aug 23 06:02:55 AM UTC 24
Finished Aug 23 06:02:58 AM UTC 24
Peak memory 212596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038712107 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_intg_err.3038712107
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all.1201374775
Short name T62
Test name
Test status
Simulation time 10036381267 ps
CPU time 58.5 seconds
Started Aug 23 06:14:56 AM UTC 24
Finished Aug 23 06:15:57 AM UTC 24
Peak memory 210768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201374775 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all.1201374775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_intg_err.206883530
Short name T128
Test name
Test status
Simulation time 241412664 ps
CPU time 2.21 seconds
Started Aug 23 06:03:18 AM UTC 24
Finished Aug 23 06:03:21 AM UTC 24
Peak memory 212684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206883530 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_intg_err.206883530
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3188944043
Short name T851
Test name
Test status
Simulation time 50394075 ps
CPU time 1.1 seconds
Started Aug 23 06:02:52 AM UTC 24
Finished Aug 23 06:02:54 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188944043 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_aliasing.3188944043
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.4189376827
Short name T863
Test name
Test status
Simulation time 2971223305 ps
CPU time 11.8 seconds
Started Aug 23 06:02:52 AM UTC 24
Finished Aug 23 06:03:05 AM UTC 24
Peak memory 212676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189376827 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_bit_bash.4189376827
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.3144325465
Short name T852
Test name
Test status
Simulation time 96215643 ps
CPU time 1.15 seconds
Started Aug 23 06:02:53 AM UTC 24
Finished Aug 23 06:02:55 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3144325465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.clkmgr_csr_mem_rw_with_rand_reset.3144325465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_rw.1637387726
Short name T98
Test name
Test status
Simulation time 60597356 ps
CPU time 0.85 seconds
Started Aug 23 06:02:52 AM UTC 24
Finished Aug 23 06:02:54 AM UTC 24
Peak memory 211984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637387726 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_rw.1637387726
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_intr_test.968592457
Short name T849
Test name
Test status
Simulation time 56717716 ps
CPU time 0.67 seconds
Started Aug 23 06:02:50 AM UTC 24
Finished Aug 23 06:02:51 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968592457 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_intr_test.968592457
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.2275648145
Short name T99
Test name
Test status
Simulation time 86264871 ps
CPU time 0.96 seconds
Started Aug 23 06:02:53 AM UTC 24
Finished Aug 23 06:02:55 AM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275
648145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_same_csr_outstanding.2275648145
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.892416010
Short name T74
Test name
Test status
Simulation time 785970827 ps
CPU time 3.19 seconds
Started Aug 23 06:02:46 AM UTC 24
Finished Aug 23 06:02:51 AM UTC 24
Peak memory 212748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8924160
10 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors.892416010
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.2603099404
Short name T77
Test name
Test status
Simulation time 128863681 ps
CPU time 1.63 seconds
Started Aug 23 06:02:46 AM UTC 24
Finished Aug 23 06:02:49 AM UTC 24
Peak memory 221584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2603099404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_
errors_with_csr_rw.2603099404
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_errors.1533683506
Short name T850
Test name
Test status
Simulation time 319646897 ps
CPU time 2.76 seconds
Started Aug 23 06:02:49 AM UTC 24
Finished Aug 23 06:02:52 AM UTC 24
Peak memory 212740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533683506 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_errors.1533683506
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_aliasing.158019650
Short name T101
Test name
Test status
Simulation time 56927332 ps
CPU time 0.98 seconds
Started Aug 23 06:02:57 AM UTC 24
Finished Aug 23 06:02:59 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158019650 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_aliasing.158019650
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3780934956
Short name T859
Test name
Test status
Simulation time 571761625 ps
CPU time 3.84 seconds
Started Aug 23 06:02:57 AM UTC 24
Finished Aug 23 06:03:02 AM UTC 24
Peak memory 212416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780934956 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_bit_bash.3780934956
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.3780647355
Short name T855
Test name
Test status
Simulation time 32933148 ps
CPU time 0.74 seconds
Started Aug 23 06:02:56 AM UTC 24
Finished Aug 23 06:02:58 AM UTC 24
Peak memory 212344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780647355 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_hw_reset.3780647355
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.2100181437
Short name T856
Test name
Test status
Simulation time 23963055 ps
CPU time 0.88 seconds
Started Aug 23 06:02:58 AM UTC 24
Finished Aug 23 06:03:00 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2100181437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.clkmgr_csr_mem_rw_with_rand_reset.2100181437
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_rw.2326949915
Short name T100
Test name
Test status
Simulation time 171955405 ps
CPU time 1.05 seconds
Started Aug 23 06:02:56 AM UTC 24
Finished Aug 23 06:02:58 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326949915 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_rw.2326949915
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_intr_test.2286154663
Short name T853
Test name
Test status
Simulation time 29897011 ps
CPU time 0.69 seconds
Started Aug 23 06:02:55 AM UTC 24
Finished Aug 23 06:02:57 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286154663 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_intr_test.2286154663
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.1164402921
Short name T102
Test name
Test status
Simulation time 46806272 ps
CPU time 0.87 seconds
Started Aug 23 06:02:58 AM UTC 24
Finished Aug 23 06:03:00 AM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164
402921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_same_csr_outstanding.1164402921
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_errors.3515362113
Short name T854
Test name
Test status
Simulation time 261512416 ps
CPU time 2.07 seconds
Started Aug 23 06:02:54 AM UTC 24
Finished Aug 23 06:02:57 AM UTC 24
Peak memory 212468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515362113 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_errors.3515362113
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.1445897913
Short name T915
Test name
Test status
Simulation time 35106063 ps
CPU time 1 seconds
Started Aug 23 06:03:21 AM UTC 24
Finished Aug 23 06:03:23 AM UTC 24
Peak memory 211860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1445897913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.clkmgr_csr_mem_rw_with_rand_reset.1445897913
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_rw.2043088153
Short name T912
Test name
Test status
Simulation time 13774040 ps
CPU time 0.69 seconds
Started Aug 23 06:03:21 AM UTC 24
Finished Aug 23 06:03:23 AM UTC 24
Peak memory 211624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043088153 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_rw.2043088153
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_intr_test.240715761
Short name T911
Test name
Test status
Simulation time 11791244 ps
CPU time 0.61 seconds
Started Aug 23 06:03:21 AM UTC 24
Finished Aug 23 06:03:23 AM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240715761 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_intr_test.240715761
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3083670005
Short name T914
Test name
Test status
Simulation time 30877433 ps
CPU time 0.91 seconds
Started Aug 23 06:03:21 AM UTC 24
Finished Aug 23 06:03:23 AM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083
670005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_same_csr_outstanding.3083670005
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.604929363
Short name T151
Test name
Test status
Simulation time 245004088 ps
CPU time 2.53 seconds
Started Aug 23 06:03:20 AM UTC 24
Finished Aug 23 06:03:24 AM UTC 24
Peak memory 212632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=604929363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg_
errors_with_csr_rw.604929363
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_errors.1320279640
Short name T913
Test name
Test status
Simulation time 39352916 ps
CPU time 1.99 seconds
Started Aug 23 06:03:20 AM UTC 24
Finished Aug 23 06:03:23 AM UTC 24
Peak memory 212168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320279640 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_errors.1320279640
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2343543044
Short name T917
Test name
Test status
Simulation time 234567200 ps
CPU time 1.79 seconds
Started Aug 23 06:03:21 AM UTC 24
Finished Aug 23 06:03:24 AM UTC 24
Peak memory 211932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343543044 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_intg_err.2343543044
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3963799143
Short name T921
Test name
Test status
Simulation time 46932454 ps
CPU time 0.95 seconds
Started Aug 23 06:03:24 AM UTC 24
Finished Aug 23 06:03:26 AM UTC 24
Peak memory 211860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3963799143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.clkmgr_csr_mem_rw_with_rand_reset.3963799143
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_rw.1124037251
Short name T919
Test name
Test status
Simulation time 37966377 ps
CPU time 0.7 seconds
Started Aug 23 06:03:23 AM UTC 24
Finished Aug 23 06:03:24 AM UTC 24
Peak memory 212340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124037251 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_rw.1124037251
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_intr_test.1193775680
Short name T918
Test name
Test status
Simulation time 16535981 ps
CPU time 0.61 seconds
Started Aug 23 06:03:23 AM UTC 24
Finished Aug 23 06:03:24 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193775680 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_intr_test.1193775680
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.590310486
Short name T920
Test name
Test status
Simulation time 109094734 ps
CPU time 1.39 seconds
Started Aug 23 06:03:23 AM UTC 24
Finished Aug 23 06:03:25 AM UTC 24
Peak memory 211924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5903
10486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_same_csr_outstanding.590310486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.3492973976
Short name T153
Test name
Test status
Simulation time 73455034 ps
CPU time 1.31 seconds
Started Aug 23 06:03:23 AM UTC 24
Finished Aug 23 06:03:25 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492973
976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors.3492973976
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.2034628967
Short name T923
Test name
Test status
Simulation time 269363166 ps
CPU time 2.53 seconds
Started Aug 23 06:03:23 AM UTC 24
Finished Aug 23 06:03:26 AM UTC 24
Peak memory 224392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2034628967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg
_errors_with_csr_rw.2034628967
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_errors.1482488026
Short name T922
Test name
Test status
Simulation time 90305555 ps
CPU time 2.17 seconds
Started Aug 23 06:03:23 AM UTC 24
Finished Aug 23 06:03:26 AM UTC 24
Peak memory 212772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482488026 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_errors.1482488026
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_intg_err.3873206629
Short name T131
Test name
Test status
Simulation time 109242206 ps
CPU time 2.22 seconds
Started Aug 23 06:03:23 AM UTC 24
Finished Aug 23 06:03:26 AM UTC 24
Peak memory 212408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873206629 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_intg_err.3873206629
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.2727377168
Short name T929
Test name
Test status
Simulation time 89508755 ps
CPU time 1.41 seconds
Started Aug 23 06:03:25 AM UTC 24
Finished Aug 23 06:03:28 AM UTC 24
Peak memory 211432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2727377168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.clkmgr_csr_mem_rw_with_rand_reset.2727377168
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_rw.3189499158
Short name T926
Test name
Test status
Simulation time 49332936 ps
CPU time 0.79 seconds
Started Aug 23 06:03:25 AM UTC 24
Finished Aug 23 06:03:27 AM UTC 24
Peak memory 211624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189499158 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_rw.3189499158
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_intr_test.341066280
Short name T925
Test name
Test status
Simulation time 50630169 ps
CPU time 0.67 seconds
Started Aug 23 06:03:25 AM UTC 24
Finished Aug 23 06:03:27 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341066280 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_intr_test.341066280
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1028218632
Short name T928
Test name
Test status
Simulation time 99038859 ps
CPU time 1.39 seconds
Started Aug 23 06:03:25 AM UTC 24
Finished Aug 23 06:03:27 AM UTC 24
Peak memory 211948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028
218632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_same_csr_outstanding.1028218632
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.141020457
Short name T146
Test name
Test status
Simulation time 120345601 ps
CPU time 1.88 seconds
Started Aug 23 06:03:24 AM UTC 24
Finished Aug 23 06:03:27 AM UTC 24
Peak memory 211640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410204
57 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors.141020457
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.2351457061
Short name T927
Test name
Test status
Simulation time 171463270 ps
CPU time 2.53 seconds
Started Aug 23 06:03:24 AM UTC 24
Finished Aug 23 06:03:27 AM UTC 24
Peak memory 213016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2351457061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg
_errors_with_csr_rw.2351457061
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_errors.1662450445
Short name T924
Test name
Test status
Simulation time 55093759 ps
CPU time 1.4 seconds
Started Aug 23 06:03:24 AM UTC 24
Finished Aug 23 06:03:26 AM UTC 24
Peak memory 211932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662450445 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_errors.1662450445
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2314960115
Short name T195
Test name
Test status
Simulation time 116863505 ps
CPU time 1.61 seconds
Started Aug 23 06:03:24 AM UTC 24
Finished Aug 23 06:03:27 AM UTC 24
Peak memory 211892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314960115 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_intg_err.2314960115
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.1443873361
Short name T936
Test name
Test status
Simulation time 54084859 ps
CPU time 1.34 seconds
Started Aug 23 06:03:27 AM UTC 24
Finished Aug 23 06:03:30 AM UTC 24
Peak memory 211996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1443873361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.clkmgr_csr_mem_rw_with_rand_reset.1443873361
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_rw.4097129050
Short name T931
Test name
Test status
Simulation time 46134928 ps
CPU time 0.74 seconds
Started Aug 23 06:03:26 AM UTC 24
Finished Aug 23 06:03:28 AM UTC 24
Peak memory 211624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097129050 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_rw.4097129050
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_intr_test.363985986
Short name T930
Test name
Test status
Simulation time 39745402 ps
CPU time 0.66 seconds
Started Aug 23 06:03:26 AM UTC 24
Finished Aug 23 06:03:28 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363985986 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_intr_test.363985986
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2890670346
Short name T933
Test name
Test status
Simulation time 33513533 ps
CPU time 1.08 seconds
Started Aug 23 06:03:27 AM UTC 24
Finished Aug 23 06:03:29 AM UTC 24
Peak memory 211876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890
670346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_same_csr_outstanding.2890670346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2401947635
Short name T932
Test name
Test status
Simulation time 313288860 ps
CPU time 2.19 seconds
Started Aug 23 06:03:25 AM UTC 24
Finished Aug 23 06:03:28 AM UTC 24
Peak memory 222292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401947
635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors.2401947635
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.3313455226
Short name T935
Test name
Test status
Simulation time 275103331 ps
CPU time 2.44 seconds
Started Aug 23 06:03:26 AM UTC 24
Finished Aug 23 06:03:30 AM UTC 24
Peak memory 221964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3313455226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg
_errors_with_csr_rw.3313455226
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_errors.45802739
Short name T940
Test name
Test status
Simulation time 789998741 ps
CPU time 3.38 seconds
Started Aug 23 06:03:26 AM UTC 24
Finished Aug 23 06:03:31 AM UTC 24
Peak memory 212448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45802739 -assert nopostpr
oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_errors.45802739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_intg_err.1001319655
Short name T934
Test name
Test status
Simulation time 105181732 ps
CPU time 2.22 seconds
Started Aug 23 06:03:26 AM UTC 24
Finished Aug 23 06:03:29 AM UTC 24
Peak memory 212408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001319655 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_intg_err.1001319655
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2151244399
Short name T944
Test name
Test status
Simulation time 40479268 ps
CPU time 1.16 seconds
Started Aug 23 06:03:29 AM UTC 24
Finished Aug 23 06:03:31 AM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2151244399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.clkmgr_csr_mem_rw_with_rand_reset.2151244399
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_rw.672078301
Short name T938
Test name
Test status
Simulation time 44640098 ps
CPU time 0.72 seconds
Started Aug 23 06:03:29 AM UTC 24
Finished Aug 23 06:03:30 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672078301 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_rw.672078301
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_intr_test.3001726526
Short name T939
Test name
Test status
Simulation time 13860621 ps
CPU time 0.64 seconds
Started Aug 23 06:03:29 AM UTC 24
Finished Aug 23 06:03:30 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001726526 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_intr_test.3001726526
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.841627349
Short name T942
Test name
Test status
Simulation time 79641933 ps
CPU time 0.93 seconds
Started Aug 23 06:03:29 AM UTC 24
Finished Aug 23 06:03:31 AM UTC 24
Peak memory 211864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8416
27349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_same_csr_outstanding.841627349
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1945318734
Short name T152
Test name
Test status
Simulation time 303213911 ps
CPU time 2.22 seconds
Started Aug 23 06:03:27 AM UTC 24
Finished Aug 23 06:03:31 AM UTC 24
Peak memory 212756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945318
734 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors.1945318734
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.209402218
Short name T937
Test name
Test status
Simulation time 66712500 ps
CPU time 1.35 seconds
Started Aug 23 06:03:27 AM UTC 24
Finished Aug 23 06:03:30 AM UTC 24
Peak memory 228556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=209402218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg_
errors_with_csr_rw.209402218
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_errors.592785881
Short name T941
Test name
Test status
Simulation time 62791532 ps
CPU time 2.06 seconds
Started Aug 23 06:03:28 AM UTC 24
Finished Aug 23 06:03:31 AM UTC 24
Peak memory 212468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592785881 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_errors.592785881
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_intg_err.452503667
Short name T943
Test name
Test status
Simulation time 197717281 ps
CPU time 2.29 seconds
Started Aug 23 06:03:28 AM UTC 24
Finished Aug 23 06:03:31 AM UTC 24
Peak memory 212680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452503667 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_intg_err.452503667
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.1919620290
Short name T949
Test name
Test status
Simulation time 34802557 ps
CPU time 0.87 seconds
Started Aug 23 06:03:31 AM UTC 24
Finished Aug 23 06:03:33 AM UTC 24
Peak memory 211860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1919620290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.clkmgr_csr_mem_rw_with_rand_reset.1919620290
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_rw.1098864453
Short name T948
Test name
Test status
Simulation time 21436717 ps
CPU time 0.75 seconds
Started Aug 23 06:03:31 AM UTC 24
Finished Aug 23 06:03:33 AM UTC 24
Peak memory 211624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098864453 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_rw.1098864453
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_intr_test.4110454568
Short name T947
Test name
Test status
Simulation time 31484430 ps
CPU time 0.61 seconds
Started Aug 23 06:03:31 AM UTC 24
Finished Aug 23 06:03:33 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110454568 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_intr_test.4110454568
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.1172736328
Short name T950
Test name
Test status
Simulation time 97308675 ps
CPU time 1.02 seconds
Started Aug 23 06:03:31 AM UTC 24
Finished Aug 23 06:03:33 AM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172
736328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_same_csr_outstanding.1172736328
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.2042381986
Short name T946
Test name
Test status
Simulation time 160802083 ps
CPU time 2.58 seconds
Started Aug 23 06:03:29 AM UTC 24
Finished Aug 23 06:03:33 AM UTC 24
Peak memory 212636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2042381986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg
_errors_with_csr_rw.2042381986
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_errors.4003175394
Short name T955
Test name
Test status
Simulation time 404076929 ps
CPU time 3.4 seconds
Started Aug 23 06:03:30 AM UTC 24
Finished Aug 23 06:03:34 AM UTC 24
Peak memory 212772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003175394 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_errors.4003175394
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1032340079
Short name T945
Test name
Test status
Simulation time 117245738 ps
CPU time 1.51 seconds
Started Aug 23 06:03:30 AM UTC 24
Finished Aug 23 06:03:32 AM UTC 24
Peak memory 211880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032340079 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_intg_err.1032340079
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.1545313237
Short name T957
Test name
Test status
Simulation time 74773303 ps
CPU time 1.26 seconds
Started Aug 23 06:03:32 AM UTC 24
Finished Aug 23 06:03:35 AM UTC 24
Peak memory 211860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1545313237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.clkmgr_csr_mem_rw_with_rand_reset.1545313237
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_rw.879314896
Short name T954
Test name
Test status
Simulation time 55513881 ps
CPU time 0.84 seconds
Started Aug 23 06:03:32 AM UTC 24
Finished Aug 23 06:03:34 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879314896 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_rw.879314896
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_intr_test.2482844757
Short name T953
Test name
Test status
Simulation time 24386255 ps
CPU time 0.63 seconds
Started Aug 23 06:03:32 AM UTC 24
Finished Aug 23 06:03:34 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482844757 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_intr_test.2482844757
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.3993241426
Short name T956
Test name
Test status
Simulation time 26533901 ps
CPU time 0.88 seconds
Started Aug 23 06:03:32 AM UTC 24
Finished Aug 23 06:03:34 AM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993
241426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_same_csr_outstanding.3993241426
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2231392795
Short name T952
Test name
Test status
Simulation time 186251656 ps
CPU time 1.88 seconds
Started Aug 23 06:03:31 AM UTC 24
Finished Aug 23 06:03:34 AM UTC 24
Peak memory 221200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231392
795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors.2231392795
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.743747164
Short name T951
Test name
Test status
Simulation time 59624506 ps
CPU time 1.51 seconds
Started Aug 23 06:03:31 AM UTC 24
Finished Aug 23 06:03:34 AM UTC 24
Peak memory 220764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=743747164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg_
errors_with_csr_rw.743747164
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_errors.113325442
Short name T916
Test name
Test status
Simulation time 114894843 ps
CPU time 2.46 seconds
Started Aug 23 06:03:32 AM UTC 24
Finished Aug 23 06:03:36 AM UTC 24
Peak memory 212740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113325442 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_errors.113325442
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_intg_err.3074892227
Short name T960
Test name
Test status
Simulation time 250551967 ps
CPU time 1.87 seconds
Started Aug 23 06:03:32 AM UTC 24
Finished Aug 23 06:03:35 AM UTC 24
Peak memory 211892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074892227 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_intg_err.3074892227
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.811966175
Short name T965
Test name
Test status
Simulation time 97011283 ps
CPU time 1.4 seconds
Started Aug 23 06:03:35 AM UTC 24
Finished Aug 23 06:03:37 AM UTC 24
Peak memory 210240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=811966175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.clkmgr_csr_mem_rw_with_rand_reset.811966175
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_rw.301026598
Short name T959
Test name
Test status
Simulation time 25515680 ps
CPU time 0.75 seconds
Started Aug 23 06:03:33 AM UTC 24
Finished Aug 23 06:03:35 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301026598 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_rw.301026598
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_intr_test.572355403
Short name T958
Test name
Test status
Simulation time 10594321 ps
CPU time 0.57 seconds
Started Aug 23 06:03:33 AM UTC 24
Finished Aug 23 06:03:35 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572355403 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_intr_test.572355403
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.1888417577
Short name T961
Test name
Test status
Simulation time 44586241 ps
CPU time 1.14 seconds
Started Aug 23 06:03:33 AM UTC 24
Finished Aug 23 06:03:36 AM UTC 24
Peak memory 211948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888
417577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_same_csr_outstanding.1888417577
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.4081611209
Short name T963
Test name
Test status
Simulation time 225286408 ps
CPU time 1.37 seconds
Started Aug 23 06:03:33 AM UTC 24
Finished Aug 23 06:03:36 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081611
209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors.4081611209
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.845177392
Short name T967
Test name
Test status
Simulation time 392586824 ps
CPU time 2.73 seconds
Started Aug 23 06:03:33 AM UTC 24
Finished Aug 23 06:03:37 AM UTC 24
Peak memory 221976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=845177392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg_
errors_with_csr_rw.845177392
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_errors.4100216218
Short name T966
Test name
Test status
Simulation time 296045822 ps
CPU time 2.58 seconds
Started Aug 23 06:03:33 AM UTC 24
Finished Aug 23 06:03:37 AM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100216218 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_errors.4100216218
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.517324626
Short name T970
Test name
Test status
Simulation time 93990582 ps
CPU time 1.02 seconds
Started Aug 23 06:03:36 AM UTC 24
Finished Aug 23 06:03:38 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=517324626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.clkmgr_csr_mem_rw_with_rand_reset.517324626
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_rw.766347549
Short name T962
Test name
Test status
Simulation time 144794224 ps
CPU time 1.08 seconds
Started Aug 23 06:03:36 AM UTC 24
Finished Aug 23 06:03:38 AM UTC 24
Peak memory 211932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766347549 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_rw.766347549
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_intr_test.320342890
Short name T969
Test name
Test status
Simulation time 86580431 ps
CPU time 0.76 seconds
Started Aug 23 06:03:36 AM UTC 24
Finished Aug 23 06:03:38 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320342890 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_intr_test.320342890
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3229083590
Short name T971
Test name
Test status
Simulation time 51021957 ps
CPU time 1.25 seconds
Started Aug 23 06:03:36 AM UTC 24
Finished Aug 23 06:03:38 AM UTC 24
Peak memory 211928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229
083590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_same_csr_outstanding.3229083590
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.218787234
Short name T968
Test name
Test status
Simulation time 121201318 ps
CPU time 1.76 seconds
Started Aug 23 06:03:35 AM UTC 24
Finished Aug 23 06:03:37 AM UTC 24
Peak memory 228088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187872
34 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors.218787234
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.585896034
Short name T964
Test name
Test status
Simulation time 108942015 ps
CPU time 1.38 seconds
Started Aug 23 06:03:35 AM UTC 24
Finished Aug 23 06:03:37 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=585896034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg_
errors_with_csr_rw.585896034
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_errors.2154231947
Short name T974
Test name
Test status
Simulation time 119696175 ps
CPU time 1.91 seconds
Started Aug 23 06:03:36 AM UTC 24
Finished Aug 23 06:03:39 AM UTC 24
Peak memory 211904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154231947 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_errors.2154231947
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2974445646
Short name T133
Test name
Test status
Simulation time 75014300 ps
CPU time 1.61 seconds
Started Aug 23 06:03:36 AM UTC 24
Finished Aug 23 06:03:38 AM UTC 24
Peak memory 211904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974445646 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_intg_err.2974445646
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3167241347
Short name T983
Test name
Test status
Simulation time 60093718 ps
CPU time 1.15 seconds
Started Aug 23 06:03:38 AM UTC 24
Finished Aug 23 06:03:40 AM UTC 24
Peak memory 211860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3167241347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.clkmgr_csr_mem_rw_with_rand_reset.3167241347
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_rw.542513050
Short name T975
Test name
Test status
Simulation time 52265701 ps
CPU time 0.71 seconds
Started Aug 23 06:03:37 AM UTC 24
Finished Aug 23 06:03:39 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542513050 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_rw.542513050
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_intr_test.2737498116
Short name T973
Test name
Test status
Simulation time 12784853 ps
CPU time 0.62 seconds
Started Aug 23 06:03:37 AM UTC 24
Finished Aug 23 06:03:39 AM UTC 24
Peak memory 211376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737498116 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_intr_test.2737498116
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1084050092
Short name T984
Test name
Test status
Simulation time 210566944 ps
CPU time 1.44 seconds
Started Aug 23 06:03:38 AM UTC 24
Finished Aug 23 06:03:40 AM UTC 24
Peak memory 211932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084
050092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_same_csr_outstanding.1084050092
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.1470730125
Short name T972
Test name
Test status
Simulation time 72761247 ps
CPU time 1.19 seconds
Started Aug 23 06:03:36 AM UTC 24
Finished Aug 23 06:03:38 AM UTC 24
Peak memory 211648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470730
125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors.1470730125
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.708181274
Short name T976
Test name
Test status
Simulation time 102638321 ps
CPU time 1.73 seconds
Started Aug 23 06:03:36 AM UTC 24
Finished Aug 23 06:03:39 AM UTC 24
Peak memory 211696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=708181274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg_
errors_with_csr_rw.708181274
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_errors.1301103254
Short name T985
Test name
Test status
Simulation time 110985954 ps
CPU time 2.83 seconds
Started Aug 23 06:03:37 AM UTC 24
Finished Aug 23 06:03:41 AM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301103254 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_errors.1301103254
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_intg_err.4208936321
Short name T977
Test name
Test status
Simulation time 127693296 ps
CPU time 1.75 seconds
Started Aug 23 06:03:37 AM UTC 24
Finished Aug 23 06:03:40 AM UTC 24
Peak memory 211892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208936321 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_intg_err.4208936321
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1838587147
Short name T105
Test name
Test status
Simulation time 73164318 ps
CPU time 1.71 seconds
Started Aug 23 06:03:02 AM UTC 24
Finished Aug 23 06:03:04 AM UTC 24
Peak memory 211948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838587147 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_aliasing.1838587147
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.384296568
Short name T872
Test name
Test status
Simulation time 401573013 ps
CPU time 5.68 seconds
Started Aug 23 06:03:02 AM UTC 24
Finished Aug 23 06:03:08 AM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384296568 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_bit_bash.384296568
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3825124011
Short name T860
Test name
Test status
Simulation time 61690109 ps
CPU time 0.77 seconds
Started Aug 23 06:03:01 AM UTC 24
Finished Aug 23 06:03:02 AM UTC 24
Peak memory 212228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825124011 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_hw_reset.3825124011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3591328963
Short name T862
Test name
Test status
Simulation time 77826358 ps
CPU time 0.91 seconds
Started Aug 23 06:03:03 AM UTC 24
Finished Aug 23 06:03:05 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3591328963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.clkmgr_csr_mem_rw_with_rand_reset.3591328963
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_rw.3388489305
Short name T861
Test name
Test status
Simulation time 98787178 ps
CPU time 0.96 seconds
Started Aug 23 06:03:01 AM UTC 24
Finished Aug 23 06:03:02 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388489305 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_rw.3388489305
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_intr_test.3361431550
Short name T857
Test name
Test status
Simulation time 36066980 ps
CPU time 0.66 seconds
Started Aug 23 06:02:59 AM UTC 24
Finished Aug 23 06:03:01 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361431550 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_intr_test.3361431550
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.1021918727
Short name T103
Test name
Test status
Simulation time 44252371 ps
CPU time 0.96 seconds
Started Aug 23 06:03:02 AM UTC 24
Finished Aug 23 06:03:04 AM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021
918727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_same_csr_outstanding.1021918727
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.454776375
Short name T78
Test name
Test status
Simulation time 183464923 ps
CPU time 1.9 seconds
Started Aug 23 06:02:58 AM UTC 24
Finished Aug 23 06:03:01 AM UTC 24
Peak memory 220756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4547763
75 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors.454776375
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2635534209
Short name T104
Test name
Test status
Simulation time 500400278 ps
CPU time 3.69 seconds
Started Aug 23 06:02:59 AM UTC 24
Finished Aug 23 06:03:04 AM UTC 24
Peak memory 221968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2635534209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_
errors_with_csr_rw.2635534209
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_errors.2556214765
Short name T858
Test name
Test status
Simulation time 117170576 ps
CPU time 1.34 seconds
Started Aug 23 06:02:59 AM UTC 24
Finished Aug 23 06:03:02 AM UTC 24
Peak memory 212012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556214765 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_errors.2556214765
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_intg_err.627472110
Short name T127
Test name
Test status
Simulation time 1049145603 ps
CPU time 4.24 seconds
Started Aug 23 06:02:59 AM UTC 24
Finished Aug 23 06:03:05 AM UTC 24
Peak memory 212424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627472110 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_intg_err.627472110
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/20.clkmgr_intr_test.1619036443
Short name T978
Test name
Test status
Simulation time 14805748 ps
CPU time 0.62 seconds
Started Aug 23 06:03:38 AM UTC 24
Finished Aug 23 06:03:40 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619036443 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.clkmgr_intr_test.1619036443
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/21.clkmgr_intr_test.3254450637
Short name T980
Test name
Test status
Simulation time 27787347 ps
CPU time 0.63 seconds
Started Aug 23 06:03:38 AM UTC 24
Finished Aug 23 06:03:40 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254450637 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.clkmgr_intr_test.3254450637
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/22.clkmgr_intr_test.3358704562
Short name T982
Test name
Test status
Simulation time 83742047 ps
CPU time 0.78 seconds
Started Aug 23 06:03:38 AM UTC 24
Finished Aug 23 06:03:40 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358704562 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clkmgr_intr_test.3358704562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/23.clkmgr_intr_test.955329788
Short name T979
Test name
Test status
Simulation time 18345936 ps
CPU time 0.61 seconds
Started Aug 23 06:03:38 AM UTC 24
Finished Aug 23 06:03:40 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955329788 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clkmgr_intr_test.955329788
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/24.clkmgr_intr_test.3816467507
Short name T981
Test name
Test status
Simulation time 14326237 ps
CPU time 0.6 seconds
Started Aug 23 06:03:38 AM UTC 24
Finished Aug 23 06:03:40 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816467507 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clkmgr_intr_test.3816467507
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/25.clkmgr_intr_test.4006372883
Short name T986
Test name
Test status
Simulation time 13913045 ps
CPU time 0.63 seconds
Started Aug 23 06:03:39 AM UTC 24
Finished Aug 23 06:03:41 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006372883 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clkmgr_intr_test.4006372883
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/26.clkmgr_intr_test.3957302423
Short name T989
Test name
Test status
Simulation time 13355476 ps
CPU time 0.6 seconds
Started Aug 23 06:03:39 AM UTC 24
Finished Aug 23 06:03:41 AM UTC 24
Peak memory 210956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957302423 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.clkmgr_intr_test.3957302423
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/27.clkmgr_intr_test.768135034
Short name T987
Test name
Test status
Simulation time 15629860 ps
CPU time 0.59 seconds
Started Aug 23 06:03:39 AM UTC 24
Finished Aug 23 06:03:41 AM UTC 24
Peak memory 210844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768135034 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.clkmgr_intr_test.768135034
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/28.clkmgr_intr_test.3372900615
Short name T988
Test name
Test status
Simulation time 28488619 ps
CPU time 0.62 seconds
Started Aug 23 06:03:39 AM UTC 24
Finished Aug 23 06:03:41 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372900615 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clkmgr_intr_test.3372900615
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/29.clkmgr_intr_test.1757459132
Short name T992
Test name
Test status
Simulation time 27351073 ps
CPU time 0.63 seconds
Started Aug 23 06:03:39 AM UTC 24
Finished Aug 23 06:03:41 AM UTC 24
Peak memory 210480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757459132 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clkmgr_intr_test.1757459132
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_aliasing.1688365505
Short name T870
Test name
Test status
Simulation time 57834216 ps
CPU time 1.05 seconds
Started Aug 23 06:03:05 AM UTC 24
Finished Aug 23 06:03:07 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688365505 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_aliasing.1688365505
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.3040841311
Short name T885
Test name
Test status
Simulation time 1363306664 ps
CPU time 8.77 seconds
Started Aug 23 06:03:05 AM UTC 24
Finished Aug 23 06:03:15 AM UTC 24
Peak memory 212340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040841311 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_bit_bash.3040841311
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.731923033
Short name T867
Test name
Test status
Simulation time 51939322 ps
CPU time 0.77 seconds
Started Aug 23 06:03:05 AM UTC 24
Finished Aug 23 06:03:07 AM UTC 24
Peak memory 212228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731923033 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_hw_reset.731923033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.857380798
Short name T869
Test name
Test status
Simulation time 20825902 ps
CPU time 0.92 seconds
Started Aug 23 06:03:05 AM UTC 24
Finished Aug 23 06:03:07 AM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=857380798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.clkmgr_csr_mem_rw_with_rand_reset.857380798
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_rw.637286216
Short name T868
Test name
Test status
Simulation time 49985615 ps
CPU time 0.78 seconds
Started Aug 23 06:03:05 AM UTC 24
Finished Aug 23 06:03:07 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637286216 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_rw.637286216
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_intr_test.1344354799
Short name T866
Test name
Test status
Simulation time 49365405 ps
CPU time 0.63 seconds
Started Aug 23 06:03:05 AM UTC 24
Finished Aug 23 06:03:07 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344354799 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_intr_test.1344354799
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1890246480
Short name T871
Test name
Test status
Simulation time 99224792 ps
CPU time 1.32 seconds
Started Aug 23 06:03:05 AM UTC 24
Finished Aug 23 06:03:07 AM UTC 24
Peak memory 211840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890
246480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_same_csr_outstanding.1890246480
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.1619914113
Short name T80
Test name
Test status
Simulation time 76744111 ps
CPU time 1.02 seconds
Started Aug 23 06:03:03 AM UTC 24
Finished Aug 23 06:03:05 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619914
113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors.1619914113
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.307042204
Short name T143
Test name
Test status
Simulation time 89041573 ps
CPU time 1.54 seconds
Started Aug 23 06:03:03 AM UTC 24
Finished Aug 23 06:03:05 AM UTC 24
Peak memory 221184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=307042204 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_e
rrors_with_csr_rw.307042204
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_errors.3812214131
Short name T864
Test name
Test status
Simulation time 37048906 ps
CPU time 1.85 seconds
Started Aug 23 06:03:03 AM UTC 24
Finished Aug 23 06:03:06 AM UTC 24
Peak memory 212012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812214131 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_errors.3812214131
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_intg_err.3997941659
Short name T865
Test name
Test status
Simulation time 72590581 ps
CPU time 1.53 seconds
Started Aug 23 06:03:04 AM UTC 24
Finished Aug 23 06:03:06 AM UTC 24
Peak memory 211944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997941659 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_intg_err.3997941659
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/30.clkmgr_intr_test.3272528454
Short name T990
Test name
Test status
Simulation time 12906188 ps
CPU time 0.59 seconds
Started Aug 23 06:03:39 AM UTC 24
Finished Aug 23 06:03:41 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272528454 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.clkmgr_intr_test.3272528454
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/31.clkmgr_intr_test.3142684362
Short name T991
Test name
Test status
Simulation time 30564217 ps
CPU time 0.62 seconds
Started Aug 23 06:03:39 AM UTC 24
Finished Aug 23 06:03:41 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142684362 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.clkmgr_intr_test.3142684362
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/32.clkmgr_intr_test.845726024
Short name T993
Test name
Test status
Simulation time 33427091 ps
CPU time 0.63 seconds
Started Aug 23 06:03:40 AM UTC 24
Finished Aug 23 06:03:41 AM UTC 24
Peak memory 210412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845726024 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.clkmgr_intr_test.845726024
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/33.clkmgr_intr_test.3184815597
Short name T994
Test name
Test status
Simulation time 12847134 ps
CPU time 0.58 seconds
Started Aug 23 06:03:40 AM UTC 24
Finished Aug 23 06:03:41 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184815597 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.clkmgr_intr_test.3184815597
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/34.clkmgr_intr_test.2413595675
Short name T995
Test name
Test status
Simulation time 12730923 ps
CPU time 0.62 seconds
Started Aug 23 06:03:41 AM UTC 24
Finished Aug 23 06:03:42 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413595675 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clkmgr_intr_test.2413595675
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/35.clkmgr_intr_test.3640981903
Short name T996
Test name
Test status
Simulation time 20376885 ps
CPU time 0.67 seconds
Started Aug 23 06:03:41 AM UTC 24
Finished Aug 23 06:03:42 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640981903 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clkmgr_intr_test.3640981903
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/36.clkmgr_intr_test.35681582
Short name T998
Test name
Test status
Simulation time 13280120 ps
CPU time 0.65 seconds
Started Aug 23 06:03:41 AM UTC 24
Finished Aug 23 06:03:42 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35681582 -assert nopostpr
oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.clkmgr_intr_test.35681582
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/37.clkmgr_intr_test.2561450748
Short name T1000
Test name
Test status
Simulation time 41637443 ps
CPU time 0.66 seconds
Started Aug 23 06:03:41 AM UTC 24
Finished Aug 23 06:03:42 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561450748 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clkmgr_intr_test.2561450748
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/38.clkmgr_intr_test.2326086166
Short name T997
Test name
Test status
Simulation time 15884421 ps
CPU time 0.64 seconds
Started Aug 23 06:03:41 AM UTC 24
Finished Aug 23 06:03:42 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326086166 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.clkmgr_intr_test.2326086166
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/39.clkmgr_intr_test.471944084
Short name T999
Test name
Test status
Simulation time 13710154 ps
CPU time 0.59 seconds
Started Aug 23 06:03:41 AM UTC 24
Finished Aug 23 06:03:42 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471944084 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clkmgr_intr_test.471944084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1367859506
Short name T876
Test name
Test status
Simulation time 29400525 ps
CPU time 0.9 seconds
Started Aug 23 06:03:09 AM UTC 24
Finished Aug 23 06:03:10 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367859506 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_aliasing.1367859506
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.2084101512
Short name T888
Test name
Test status
Simulation time 399621911 ps
CPU time 5.64 seconds
Started Aug 23 06:03:08 AM UTC 24
Finished Aug 23 06:03:15 AM UTC 24
Peak memory 212160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084101512 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_bit_bash.2084101512
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.874187932
Short name T875
Test name
Test status
Simulation time 53489466 ps
CPU time 0.78 seconds
Started Aug 23 06:03:07 AM UTC 24
Finished Aug 23 06:03:10 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874187932 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_hw_reset.874187932
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.4118216032
Short name T879
Test name
Test status
Simulation time 143900267 ps
CPU time 1.41 seconds
Started Aug 23 06:03:10 AM UTC 24
Finished Aug 23 06:03:12 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=4118216032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.clkmgr_csr_mem_rw_with_rand_reset.4118216032
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_rw.1297466303
Short name T874
Test name
Test status
Simulation time 24099545 ps
CPU time 0.7 seconds
Started Aug 23 06:03:07 AM UTC 24
Finished Aug 23 06:03:10 AM UTC 24
Peak memory 212340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297466303 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_rw.1297466303
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_intr_test.2852290387
Short name T873
Test name
Test status
Simulation time 32890018 ps
CPU time 0.64 seconds
Started Aug 23 06:03:07 AM UTC 24
Finished Aug 23 06:03:09 AM UTC 24
Peak memory 211452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852290387 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_intr_test.2852290387
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.1385257962
Short name T878
Test name
Test status
Simulation time 43234848 ps
CPU time 1.09 seconds
Started Aug 23 06:03:10 AM UTC 24
Finished Aug 23 06:03:12 AM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385
257962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_same_csr_outstanding.1385257962
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.1892059044
Short name T79
Test name
Test status
Simulation time 74367249 ps
CPU time 1.32 seconds
Started Aug 23 06:03:06 AM UTC 24
Finished Aug 23 06:03:08 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892059
044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors.1892059044
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.725608661
Short name T144
Test name
Test status
Simulation time 94058550 ps
CPU time 1.68 seconds
Started Aug 23 06:03:06 AM UTC 24
Finished Aug 23 06:03:09 AM UTC 24
Peak memory 228828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=725608661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_e
rrors_with_csr_rw.725608661
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_errors.867533757
Short name T877
Test name
Test status
Simulation time 204321551 ps
CPU time 2.54 seconds
Started Aug 23 06:03:07 AM UTC 24
Finished Aug 23 06:03:11 AM UTC 24
Peak memory 212784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867533757 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_errors.867533757
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_intg_err.30619925
Short name T134
Test name
Test status
Simulation time 133306103 ps
CPU time 1.5 seconds
Started Aug 23 06:03:07 AM UTC 24
Finished Aug 23 06:03:10 AM UTC 24
Peak memory 211940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30619925 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_intg_err.30619925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/40.clkmgr_intr_test.190928111
Short name T1001
Test name
Test status
Simulation time 20025957 ps
CPU time 0.59 seconds
Started Aug 23 06:03:41 AM UTC 24
Finished Aug 23 06:03:42 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190928111 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.clkmgr_intr_test.190928111
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/41.clkmgr_intr_test.1520619860
Short name T1002
Test name
Test status
Simulation time 24969874 ps
CPU time 0.61 seconds
Started Aug 23 06:03:42 AM UTC 24
Finished Aug 23 06:03:44 AM UTC 24
Peak memory 209440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520619860 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clkmgr_intr_test.1520619860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/42.clkmgr_intr_test.995349061
Short name T1006
Test name
Test status
Simulation time 26362065 ps
CPU time 0.64 seconds
Started Aug 23 06:03:42 AM UTC 24
Finished Aug 23 06:03:44 AM UTC 24
Peak memory 209380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995349061 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.clkmgr_intr_test.995349061
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/43.clkmgr_intr_test.3139977084
Short name T1005
Test name
Test status
Simulation time 14162096 ps
CPU time 0.63 seconds
Started Aug 23 06:03:42 AM UTC 24
Finished Aug 23 06:03:44 AM UTC 24
Peak memory 211440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139977084 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.clkmgr_intr_test.3139977084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/44.clkmgr_intr_test.2651899578
Short name T1007
Test name
Test status
Simulation time 36662599 ps
CPU time 0.64 seconds
Started Aug 23 06:03:42 AM UTC 24
Finished Aug 23 06:03:44 AM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651899578 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.clkmgr_intr_test.2651899578
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/45.clkmgr_intr_test.538939651
Short name T1003
Test name
Test status
Simulation time 13335802 ps
CPU time 0.6 seconds
Started Aug 23 06:03:42 AM UTC 24
Finished Aug 23 06:03:44 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538939651 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.clkmgr_intr_test.538939651
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/46.clkmgr_intr_test.2880319326
Short name T1004
Test name
Test status
Simulation time 12839875 ps
CPU time 0.59 seconds
Started Aug 23 06:03:42 AM UTC 24
Finished Aug 23 06:03:44 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880319326 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.clkmgr_intr_test.2880319326
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/47.clkmgr_intr_test.3629037690
Short name T1008
Test name
Test status
Simulation time 15813394 ps
CPU time 0.67 seconds
Started Aug 23 06:03:42 AM UTC 24
Finished Aug 23 06:03:44 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629037690 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clkmgr_intr_test.3629037690
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/48.clkmgr_intr_test.4127188351
Short name T1009
Test name
Test status
Simulation time 25871862 ps
CPU time 0.62 seconds
Started Aug 23 06:03:42 AM UTC 24
Finished Aug 23 06:03:44 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127188351 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.clkmgr_intr_test.4127188351
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/49.clkmgr_intr_test.1739461019
Short name T1010
Test name
Test status
Simulation time 19801319 ps
CPU time 0.65 seconds
Started Aug 23 06:03:42 AM UTC 24
Finished Aug 23 06:03:44 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739461019 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.clkmgr_intr_test.1739461019
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.2013544843
Short name T887
Test name
Test status
Simulation time 82093696 ps
CPU time 0.98 seconds
Started Aug 23 06:03:13 AM UTC 24
Finished Aug 23 06:03:15 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2013544843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.clkmgr_csr_mem_rw_with_rand_reset.2013544843
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_rw.1416275606
Short name T881
Test name
Test status
Simulation time 34261605 ps
CPU time 0.68 seconds
Started Aug 23 06:03:11 AM UTC 24
Finished Aug 23 06:03:12 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416275606 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_rw.1416275606
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_intr_test.1464608065
Short name T880
Test name
Test status
Simulation time 18617460 ps
CPU time 0.59 seconds
Started Aug 23 06:03:11 AM UTC 24
Finished Aug 23 06:03:12 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464608065 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_intr_test.1464608065
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.3255611299
Short name T883
Test name
Test status
Simulation time 327354335 ps
CPU time 1.72 seconds
Started Aug 23 06:03:12 AM UTC 24
Finished Aug 23 06:03:15 AM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255
611299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_same_csr_outstanding.3255611299
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.580896161
Short name T138
Test name
Test status
Simulation time 101919875 ps
CPU time 1.6 seconds
Started Aug 23 06:03:10 AM UTC 24
Finished Aug 23 06:03:12 AM UTC 24
Peak memory 227580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5808961
61 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors.580896161
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.1128131101
Short name T149
Test name
Test status
Simulation time 293849114 ps
CPU time 2.67 seconds
Started Aug 23 06:03:10 AM UTC 24
Finished Aug 23 06:03:13 AM UTC 24
Peak memory 212932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1128131101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_
errors_with_csr_rw.1128131101
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_errors.3664388052
Short name T884
Test name
Test status
Simulation time 272370979 ps
CPU time 3.14 seconds
Started Aug 23 06:03:11 AM UTC 24
Finished Aug 23 06:03:15 AM UTC 24
Peak memory 212804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664388052 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_errors.3664388052
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_intg_err.2756652031
Short name T882
Test name
Test status
Simulation time 189286688 ps
CPU time 1.56 seconds
Started Aug 23 06:03:11 AM UTC 24
Finished Aug 23 06:03:13 AM UTC 24
Peak memory 211936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756652031 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_intg_err.2756652031
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.1283909716
Short name T891
Test name
Test status
Simulation time 89301792 ps
CPU time 1.17 seconds
Started Aug 23 06:03:14 AM UTC 24
Finished Aug 23 06:03:16 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1283909716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.clkmgr_csr_mem_rw_with_rand_reset.1283909716
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_rw.2632207733
Short name T889
Test name
Test status
Simulation time 38642945 ps
CPU time 0.7 seconds
Started Aug 23 06:03:14 AM UTC 24
Finished Aug 23 06:03:16 AM UTC 24
Peak memory 211984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632207733 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_rw.2632207733
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_intr_test.2902873663
Short name T886
Test name
Test status
Simulation time 16470335 ps
CPU time 0.6 seconds
Started Aug 23 06:03:13 AM UTC 24
Finished Aug 23 06:03:15 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902873663 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_intr_test.2902873663
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.4054577191
Short name T892
Test name
Test status
Simulation time 210712451 ps
CPU time 1.75 seconds
Started Aug 23 06:03:14 AM UTC 24
Finished Aug 23 06:03:17 AM UTC 24
Peak memory 211944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054
577191 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_same_csr_outstanding.4054577191
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1258821112
Short name T140
Test name
Test status
Simulation time 211998256 ps
CPU time 1.73 seconds
Started Aug 23 06:03:13 AM UTC 24
Finished Aug 23 06:03:16 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258821
112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors.1258821112
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.3808089389
Short name T139
Test name
Test status
Simulation time 59053893 ps
CPU time 1.48 seconds
Started Aug 23 06:03:13 AM UTC 24
Finished Aug 23 06:03:16 AM UTC 24
Peak memory 221196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3808089389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_
errors_with_csr_rw.3808089389
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_errors.751024944
Short name T890
Test name
Test status
Simulation time 64975657 ps
CPU time 1.68 seconds
Started Aug 23 06:03:13 AM UTC 24
Finished Aug 23 06:03:16 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751024944 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_errors.751024944
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_intg_err.622273547
Short name T130
Test name
Test status
Simulation time 204161430 ps
CPU time 2.48 seconds
Started Aug 23 06:03:13 AM UTC 24
Finished Aug 23 06:03:17 AM UTC 24
Peak memory 212360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622273547 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_intg_err.622273547
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1960322454
Short name T898
Test name
Test status
Simulation time 94666660 ps
CPU time 1.1 seconds
Started Aug 23 06:03:17 AM UTC 24
Finished Aug 23 06:03:19 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1960322454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.clkmgr_csr_mem_rw_with_rand_reset.1960322454
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_rw.1992559582
Short name T896
Test name
Test status
Simulation time 49001521 ps
CPU time 0.74 seconds
Started Aug 23 06:03:17 AM UTC 24
Finished Aug 23 06:03:18 AM UTC 24
Peak memory 211924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992559582 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_rw.1992559582
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_intr_test.2348766901
Short name T895
Test name
Test status
Simulation time 13244487 ps
CPU time 0.61 seconds
Started Aug 23 06:03:17 AM UTC 24
Finished Aug 23 06:03:18 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348766901 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_intr_test.2348766901
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.480618285
Short name T897
Test name
Test status
Simulation time 61707924 ps
CPU time 0.89 seconds
Started Aug 23 06:03:17 AM UTC 24
Finished Aug 23 06:03:18 AM UTC 24
Peak memory 211872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4806
18285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_same_csr_outstanding.480618285
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2657291762
Short name T147
Test name
Test status
Simulation time 52637834 ps
CPU time 1.12 seconds
Started Aug 23 06:03:15 AM UTC 24
Finished Aug 23 06:03:17 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657291
762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors.2657291762
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.851221322
Short name T150
Test name
Test status
Simulation time 482449541 ps
CPU time 3.41 seconds
Started Aug 23 06:03:15 AM UTC 24
Finished Aug 23 06:03:20 AM UTC 24
Peak memory 221968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=851221322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_e
rrors_with_csr_rw.851221322
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_errors.4178661073
Short name T893
Test name
Test status
Simulation time 53564835 ps
CPU time 1.41 seconds
Started Aug 23 06:03:15 AM UTC 24
Finished Aug 23 06:03:18 AM UTC 24
Peak memory 212012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178661073 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_errors.4178661073
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_intg_err.1322406647
Short name T894
Test name
Test status
Simulation time 51562362 ps
CPU time 1.36 seconds
Started Aug 23 06:03:15 AM UTC 24
Finished Aug 23 06:03:18 AM UTC 24
Peak memory 211876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322406647 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_intg_err.1322406647
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2913123663
Short name T904
Test name
Test status
Simulation time 30221377 ps
CPU time 0.92 seconds
Started Aug 23 06:03:19 AM UTC 24
Finished Aug 23 06:03:21 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2913123663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.clkmgr_csr_mem_rw_with_rand_reset.2913123663
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_rw.3372370637
Short name T901
Test name
Test status
Simulation time 222714698 ps
CPU time 1.14 seconds
Started Aug 23 06:03:18 AM UTC 24
Finished Aug 23 06:03:20 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372370637 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_rw.3372370637
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_intr_test.844574705
Short name T900
Test name
Test status
Simulation time 31038064 ps
CPU time 0.59 seconds
Started Aug 23 06:03:18 AM UTC 24
Finished Aug 23 06:03:19 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844574705 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_intr_test.844574705
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.2395354628
Short name T902
Test name
Test status
Simulation time 162456343 ps
CPU time 1.46 seconds
Started Aug 23 06:03:18 AM UTC 24
Finished Aug 23 06:03:20 AM UTC 24
Peak memory 211924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395
354628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_same_csr_outstanding.2395354628
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.2743627875
Short name T148
Test name
Test status
Simulation time 234223953 ps
CPU time 2.15 seconds
Started Aug 23 06:03:17 AM UTC 24
Finished Aug 23 06:03:20 AM UTC 24
Peak memory 229224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743627
875 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors.2743627875
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.1470414462
Short name T141
Test name
Test status
Simulation time 253754068 ps
CPU time 1.9 seconds
Started Aug 23 06:03:17 AM UTC 24
Finished Aug 23 06:03:20 AM UTC 24
Peak memory 211648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1470414462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_
errors_with_csr_rw.1470414462
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_errors.675759430
Short name T899
Test name
Test status
Simulation time 68999685 ps
CPU time 1.16 seconds
Started Aug 23 06:03:17 AM UTC 24
Finished Aug 23 06:03:19 AM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675759430 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_errors.675759430
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.1649261852
Short name T910
Test name
Test status
Simulation time 89586076 ps
CPU time 1.08 seconds
Started Aug 23 06:03:20 AM UTC 24
Finished Aug 23 06:03:22 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1649261852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.clkmgr_csr_mem_rw_with_rand_reset.1649261852
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_rw.3808455118
Short name T907
Test name
Test status
Simulation time 15085178 ps
CPU time 0.67 seconds
Started Aug 23 06:03:20 AM UTC 24
Finished Aug 23 06:03:22 AM UTC 24
Peak memory 212284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808455118 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_rw.3808455118
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_intr_test.4004296333
Short name T903
Test name
Test status
Simulation time 13189314 ps
CPU time 0.59 seconds
Started Aug 23 06:03:19 AM UTC 24
Finished Aug 23 06:03:21 AM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004296333 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_intr_test.4004296333
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3535400289
Short name T908
Test name
Test status
Simulation time 22624986 ps
CPU time 0.86 seconds
Started Aug 23 06:03:20 AM UTC 24
Finished Aug 23 06:03:22 AM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535
400289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_same_csr_outstanding.3535400289
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.7831100
Short name T154
Test name
Test status
Simulation time 58113899 ps
CPU time 1.2 seconds
Started Aug 23 06:03:19 AM UTC 24
Finished Aug 23 06:03:21 AM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7831100
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors.7831100
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.3498043297
Short name T909
Test name
Test status
Simulation time 272260108 ps
CPU time 2.07 seconds
Started Aug 23 06:03:19 AM UTC 24
Finished Aug 23 06:03:22 AM UTC 24
Peak memory 222240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3498043297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_
errors_with_csr_rw.3498043297
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_errors.2262428141
Short name T905
Test name
Test status
Simulation time 96789455 ps
CPU time 1.57 seconds
Started Aug 23 06:03:19 AM UTC 24
Finished Aug 23 06:03:22 AM UTC 24
Peak memory 211996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262428141 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_errors.2262428141
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2702125514
Short name T906
Test name
Test status
Simulation time 94256670 ps
CPU time 1.56 seconds
Started Aug 23 06:03:19 AM UTC 24
Finished Aug 23 06:03:22 AM UTC 24
Peak memory 211884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702125514 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_intg_err.2702125514
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_div_intersig_mubi.867861318
Short name T33
Test name
Test status
Simulation time 42764575 ps
CPU time 0.76 seconds
Started Aug 23 06:13:30 AM UTC 24
Finished Aug 23 06:13:32 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867861318 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_div_intersig_mubi.867861318
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_extclk.3974499969
Short name T5
Test name
Test status
Simulation time 111917267 ps
CPU time 1.02 seconds
Started Aug 23 06:13:25 AM UTC 24
Finished Aug 23 06:13:27 AM UTC 24
Peak memory 209856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974499969 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.3974499969
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency.3179381234
Short name T3
Test name
Test status
Simulation time 1639118128 ps
CPU time 12.96 seconds
Started Aug 23 06:13:25 AM UTC 24
Finished Aug 23 06:13:39 AM UTC 24
Peak memory 210348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179381234 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.3179381234
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_idle_intersig_mubi.2217640942
Short name T32
Test name
Test status
Simulation time 31098211 ps
CPU time 0.86 seconds
Started Aug 23 06:13:29 AM UTC 24
Finished Aug 23 06:13:31 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217640942 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_idle_intersig_mubi.2217640942
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.1462288321
Short name T31
Test name
Test status
Simulation time 25691227 ps
CPU time 0.8 seconds
Started Aug 23 06:13:29 AM UTC 24
Finished Aug 23 06:13:31 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462288321
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_clk_byp_req_intersig_mubi.1462288321
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_peri.397603456
Short name T6
Test name
Test status
Simulation time 167881499 ps
CPU time 1.02 seconds
Started Aug 23 06:13:27 AM UTC 24
Finished Aug 23 06:13:29 AM UTC 24
Peak memory 210212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397603456 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.397603456
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_regwen.1795166282
Short name T2
Test name
Test status
Simulation time 937180555 ps
CPU time 3.49 seconds
Started Aug 23 06:13:30 AM UTC 24
Finished Aug 23 06:13:35 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795166282 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.1795166282
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all_with_rand_reset.858547862
Short name T15
Test name
Test status
Simulation time 8156703071 ps
CPU time 41.81 seconds
Started Aug 23 06:13:32 AM UTC 24
Finished Aug 23 06:14:15 AM UTC 24
Peak memory 226816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858547862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.858547862
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/0.clkmgr_trans.2250958503
Short name T29
Test name
Test status
Simulation time 40660616 ps
CPU time 0.81 seconds
Started Aug 23 06:13:28 AM UTC 24
Finished Aug 23 06:13:30 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250958503 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.2250958503
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/0.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_alert_test.2392298707
Short name T20
Test name
Test status
Simulation time 17555606 ps
CPU time 0.73 seconds
Started Aug 23 06:13:39 AM UTC 24
Finished Aug 23 06:13:40 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392298707 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_alert_test.2392298707
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.2606463798
Short name T70
Test name
Test status
Simulation time 27952023 ps
CPU time 0.71 seconds
Started Aug 23 06:13:35 AM UTC 24
Finished Aug 23 06:13:37 AM UTC 24
Peak memory 210044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606463798 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_handshake_intersig_mubi.2606463798
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_status.3452551015
Short name T61
Test name
Test status
Simulation time 17663681 ps
CPU time 0.65 seconds
Started Aug 23 06:13:35 AM UTC 24
Finished Aug 23 06:13:37 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452551015 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.3452551015
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_div_intersig_mubi.576469373
Short name T73
Test name
Test status
Simulation time 40761486 ps
CPU time 0.8 seconds
Started Aug 23 06:13:36 AM UTC 24
Finished Aug 23 06:13:38 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576469373 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_div_intersig_mubi.576469373
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_extclk.3433521764
Short name T52
Test name
Test status
Simulation time 13019127 ps
CPU time 0.66 seconds
Started Aug 23 06:13:33 AM UTC 24
Finished Aug 23 06:13:34 AM UTC 24
Peak memory 210504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433521764 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.3433521764
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency_timeout.1898316993
Short name T21
Test name
Test status
Simulation time 1220409563 ps
CPU time 6.49 seconds
Started Aug 23 06:13:33 AM UTC 24
Finished Aug 23 06:13:40 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898316993 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_timeout.1898316993
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.2491417743
Short name T72
Test name
Test status
Simulation time 189907968 ps
CPU time 1.19 seconds
Started Aug 23 06:13:35 AM UTC 24
Finished Aug 23 06:13:37 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491417743
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_lc_clk_byp_req_intersig_mubi.2491417743
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.3755056331
Short name T69
Test name
Test status
Simulation time 19537472 ps
CPU time 0.72 seconds
Started Aug 23 06:13:35 AM UTC 24
Finished Aug 23 06:13:37 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755056331
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_lc_ctrl_intersig_mubi.3755056331
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_peri.2875312608
Short name T56
Test name
Test status
Simulation time 26082867 ps
CPU time 0.75 seconds
Started Aug 23 06:13:34 AM UTC 24
Finished Aug 23 06:13:36 AM UTC 24
Peak memory 209900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875312608 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.2875312608
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_regwen.2646221998
Short name T11
Test name
Test status
Simulation time 1298129296 ps
CPU time 5.25 seconds
Started Aug 23 06:13:37 AM UTC 24
Finished Aug 23 06:13:44 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646221998 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.2646221998
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_sec_cm.2256236263
Short name T19
Test name
Test status
Simulation time 204412531 ps
CPU time 1.86 seconds
Started Aug 23 06:13:37 AM UTC 24
Finished Aug 23 06:13:40 AM UTC 24
Peak memory 242012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256236263 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_sec_cm.2256236263
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_smoke.813448090
Short name T53
Test name
Test status
Simulation time 16363377 ps
CPU time 0.72 seconds
Started Aug 23 06:13:33 AM UTC 24
Finished Aug 23 06:13:34 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813448090 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.813448090
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all.2519011086
Short name T95
Test name
Test status
Simulation time 3142165341 ps
CPU time 22.15 seconds
Started Aug 23 06:13:38 AM UTC 24
Finished Aug 23 06:14:01 AM UTC 24
Peak memory 210984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519011086 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all.2519011086
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all_with_rand_reset.2863931907
Short name T81
Test name
Test status
Simulation time 11716753844 ps
CPU time 74.23 seconds
Started Aug 23 06:13:38 AM UTC 24
Finished Aug 23 06:14:53 AM UTC 24
Peak memory 220196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863931907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.2863931907
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/1.clkmgr_trans.1617995922
Short name T57
Test name
Test status
Simulation time 127390533 ps
CPU time 1.15 seconds
Started Aug 23 06:13:34 AM UTC 24
Finished Aug 23 06:13:36 AM UTC 24
Peak memory 209704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617995922 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.1617995922
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/1.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/10.clkmgr_alert_test.3755006418
Short name T260
Test name
Test status
Simulation time 18144671 ps
CPU time 0.71 seconds
Started Aug 23 06:14:40 AM UTC 24
Finished Aug 23 06:14:43 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755006418 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_alert_test.3755006418
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_status.61263510
Short name T193
Test name
Test status
Simulation time 17587456 ps
CPU time 0.65 seconds
Started Aug 23 06:14:36 AM UTC 24
Finished Aug 23 06:14:37 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61263510 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.61263510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/10.clkmgr_div_intersig_mubi.715449754
Short name T257
Test name
Test status
Simulation time 25713983 ps
CPU time 0.67 seconds
Started Aug 23 06:14:38 AM UTC 24
Finished Aug 23 06:14:40 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715449754 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_div_intersig_mubi.715449754
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/10.clkmgr_extclk.30395279
Short name T250
Test name
Test status
Simulation time 29614860 ps
CPU time 0.85 seconds
Started Aug 23 06:14:35 AM UTC 24
Finished Aug 23 06:14:37 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30395279 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.30395279
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency.1206771128
Short name T14
Test name
Test status
Simulation time 805279350 ps
CPU time 4.63 seconds
Started Aug 23 06:14:35 AM UTC 24
Finished Aug 23 06:14:41 AM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206771128 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.1206771128
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency_timeout.1212743674
Short name T258
Test name
Test status
Simulation time 621938785 ps
CPU time 4.72 seconds
Started Aug 23 06:14:35 AM UTC 24
Finished Aug 23 06:14:41 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212743674 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_timeout.1212743674
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/10.clkmgr_idle_intersig_mubi.834038408
Short name T256
Test name
Test status
Simulation time 14330990 ps
CPU time 0.68 seconds
Started Aug 23 06:14:38 AM UTC 24
Finished Aug 23 06:14:40 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834038408 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_idle_intersig_mubi.834038408
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.677558763
Short name T254
Test name
Test status
Simulation time 15037235 ps
CPU time 0.65 seconds
Started Aug 23 06:14:38 AM UTC 24
Finished Aug 23 06:14:40 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677558763 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_lc_clk_byp_req_intersig_mubi.677558763
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.826239662
Short name T255
Test name
Test status
Simulation time 29091731 ps
CPU time 0.73 seconds
Started Aug 23 06:14:38 AM UTC 24
Finished Aug 23 06:14:40 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826239662 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_lc_ctrl_intersig_mubi.826239662
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/10.clkmgr_peri.549940142
Short name T249
Test name
Test status
Simulation time 44382373 ps
CPU time 0.74 seconds
Started Aug 23 06:14:35 AM UTC 24
Finished Aug 23 06:14:37 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549940142 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.549940142
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/10.clkmgr_regwen.4194997665
Short name T259
Test name
Test status
Simulation time 433873991 ps
CPU time 1.98 seconds
Started Aug 23 06:14:38 AM UTC 24
Finished Aug 23 06:14:41 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194997665 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.4194997665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/10.clkmgr_smoke.1425348430
Short name T248
Test name
Test status
Simulation time 31402066 ps
CPU time 0.74 seconds
Started Aug 23 06:14:33 AM UTC 24
Finished Aug 23 06:14:35 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425348430 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.1425348430
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all.2112566617
Short name T300
Test name
Test status
Simulation time 3398167526 ps
CPU time 21.88 seconds
Started Aug 23 06:14:40 AM UTC 24
Finished Aug 23 06:15:04 AM UTC 24
Peak memory 209100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112566617 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all.2112566617
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all_with_rand_reset.284072587
Short name T84
Test name
Test status
Simulation time 6184660008 ps
CPU time 36.84 seconds
Started Aug 23 06:14:39 AM UTC 24
Finished Aug 23 06:15:18 AM UTC 24
Peak memory 224388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284072587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.284072587
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/10.clkmgr_trans.3059367378
Short name T253
Test name
Test status
Simulation time 16024923 ps
CPU time 0.65 seconds
Started Aug 23 06:14:36 AM UTC 24
Finished Aug 23 06:14:38 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059367378 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.3059367378
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/10.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/11.clkmgr_alert_test.469721724
Short name T272
Test name
Test status
Simulation time 34821408 ps
CPU time 0.66 seconds
Started Aug 23 06:14:46 AM UTC 24
Finished Aug 23 06:14:48 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469721724 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_alert_test.469721724
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.3216587450
Short name T269
Test name
Test status
Simulation time 254860413 ps
CPU time 1.38 seconds
Started Aug 23 06:14:44 AM UTC 24
Finished Aug 23 06:14:47 AM UTC 24
Peak memory 209012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216587450 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_handshake_intersig_mubi.3216587450
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_status.3959498224
Short name T263
Test name
Test status
Simulation time 31380019 ps
CPU time 0.65 seconds
Started Aug 23 06:14:42 AM UTC 24
Finished Aug 23 06:14:44 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959498224 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.3959498224
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/11.clkmgr_div_intersig_mubi.4079371408
Short name T270
Test name
Test status
Simulation time 162189291 ps
CPU time 1.1 seconds
Started Aug 23 06:14:45 AM UTC 24
Finished Aug 23 06:14:47 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079371408 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_div_intersig_mubi.4079371408
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/11.clkmgr_extclk.2906090175
Short name T261
Test name
Test status
Simulation time 64111286 ps
CPU time 0.77 seconds
Started Aug 23 06:14:40 AM UTC 24
Finished Aug 23 06:14:43 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906090175 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.2906090175
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency.3328659073
Short name T281
Test name
Test status
Simulation time 1275402632 ps
CPU time 9.66 seconds
Started Aug 23 06:14:41 AM UTC 24
Finished Aug 23 06:14:52 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328659073 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.3328659073
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency_timeout.2294238682
Short name T278
Test name
Test status
Simulation time 1223805205 ps
CPU time 8.48 seconds
Started Aug 23 06:14:41 AM UTC 24
Finished Aug 23 06:14:51 AM UTC 24
Peak memory 210644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294238682 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_timeout.2294238682
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/11.clkmgr_idle_intersig_mubi.2500744199
Short name T266
Test name
Test status
Simulation time 91284533 ps
CPU time 0.9 seconds
Started Aug 23 06:14:42 AM UTC 24
Finished Aug 23 06:14:44 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500744199 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_idle_intersig_mubi.2500744199
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.2117358676
Short name T267
Test name
Test status
Simulation time 19954207 ps
CPU time 0.72 seconds
Started Aug 23 06:14:44 AM UTC 24
Finished Aug 23 06:14:46 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117358676
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_lc_clk_byp_req_intersig_mubi.2117358676
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.845806582
Short name T268
Test name
Test status
Simulation time 60745418 ps
CPU time 0.84 seconds
Started Aug 23 06:14:44 AM UTC 24
Finished Aug 23 06:14:46 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845806582 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_lc_ctrl_intersig_mubi.845806582
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/11.clkmgr_peri.2344227162
Short name T264
Test name
Test status
Simulation time 25497845 ps
CPU time 0.69 seconds
Started Aug 23 06:14:42 AM UTC 24
Finished Aug 23 06:14:44 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344227162 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.2344227162
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/11.clkmgr_smoke.173809324
Short name T262
Test name
Test status
Simulation time 57959413 ps
CPU time 0.83 seconds
Started Aug 23 06:14:40 AM UTC 24
Finished Aug 23 06:14:43 AM UTC 24
Peak memory 209428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173809324 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.173809324
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all.289650623
Short name T316
Test name
Test status
Simulation time 2943861904 ps
CPU time 22.59 seconds
Started Aug 23 06:14:45 AM UTC 24
Finished Aug 23 06:15:09 AM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289650623 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all.289650623
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all_with_rand_reset.2611184280
Short name T166
Test name
Test status
Simulation time 4045825084 ps
CPU time 51.93 seconds
Started Aug 23 06:14:45 AM UTC 24
Finished Aug 23 06:15:39 AM UTC 24
Peak memory 220480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611184280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.2611184280
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/11.clkmgr_trans.335750707
Short name T265
Test name
Test status
Simulation time 12904148 ps
CPU time 0.64 seconds
Started Aug 23 06:14:42 AM UTC 24
Finished Aug 23 06:14:44 AM UTC 24
Peak memory 210116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335750707 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.335750707
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/11.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/12.clkmgr_alert_test.4180871449
Short name T283
Test name
Test status
Simulation time 15028297 ps
CPU time 0.66 seconds
Started Aug 23 06:14:51 AM UTC 24
Finished Aug 23 06:14:53 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180871449 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_alert_test.4180871449
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.796017787
Short name T280
Test name
Test status
Simulation time 75038352 ps
CPU time 0.9 seconds
Started Aug 23 06:14:49 AM UTC 24
Finished Aug 23 06:14:51 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796017787 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_handshake_intersig_mubi.796017787
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_status.2046682110
Short name T274
Test name
Test status
Simulation time 27838140 ps
CPU time 0.64 seconds
Started Aug 23 06:14:49 AM UTC 24
Finished Aug 23 06:14:51 AM UTC 24
Peak memory 208904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046682110 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.2046682110
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/12.clkmgr_div_intersig_mubi.2741509261
Short name T282
Test name
Test status
Simulation time 22167152 ps
CPU time 0.74 seconds
Started Aug 23 06:14:51 AM UTC 24
Finished Aug 23 06:14:53 AM UTC 24
Peak memory 209564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741509261 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_div_intersig_mubi.2741509261
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/12.clkmgr_extclk.950829273
Short name T271
Test name
Test status
Simulation time 15415654 ps
CPU time 0.66 seconds
Started Aug 23 06:14:46 AM UTC 24
Finished Aug 23 06:14:48 AM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950829273 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.950829273
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency.205353884
Short name T286
Test name
Test status
Simulation time 1682171121 ps
CPU time 6.3 seconds
Started Aug 23 06:14:47 AM UTC 24
Finished Aug 23 06:14:55 AM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205353884 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.205353884
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency_timeout.3664754648
Short name T289
Test name
Test status
Simulation time 974501403 ps
CPU time 7.22 seconds
Started Aug 23 06:14:47 AM UTC 24
Finished Aug 23 06:14:56 AM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664754648 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_timeout.3664754648
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/12.clkmgr_idle_intersig_mubi.2481471778
Short name T275
Test name
Test status
Simulation time 16069697 ps
CPU time 0.68 seconds
Started Aug 23 06:14:49 AM UTC 24
Finished Aug 23 06:14:51 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481471778 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_idle_intersig_mubi.2481471778
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.3978757902
Short name T279
Test name
Test status
Simulation time 79929254 ps
CPU time 0.89 seconds
Started Aug 23 06:14:49 AM UTC 24
Finished Aug 23 06:14:51 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978757902
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_lc_clk_byp_req_intersig_mubi.3978757902
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.3318376579
Short name T276
Test name
Test status
Simulation time 22021920 ps
CPU time 0.73 seconds
Started Aug 23 06:14:49 AM UTC 24
Finished Aug 23 06:14:51 AM UTC 24
Peak memory 209004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318376579
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_lc_ctrl_intersig_mubi.3318376579
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/12.clkmgr_peri.2604799116
Short name T273
Test name
Test status
Simulation time 20965878 ps
CPU time 0.65 seconds
Started Aug 23 06:14:49 AM UTC 24
Finished Aug 23 06:14:50 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604799116 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.2604799116
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/12.clkmgr_regwen.2414626084
Short name T135
Test name
Test status
Simulation time 581729841 ps
CPU time 2.12 seconds
Started Aug 23 06:14:51 AM UTC 24
Finished Aug 23 06:14:54 AM UTC 24
Peak memory 210168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414626084 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.2414626084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/12.clkmgr_smoke.2108566098
Short name T157
Test name
Test status
Simulation time 137799492 ps
CPU time 1.02 seconds
Started Aug 23 06:14:46 AM UTC 24
Finished Aug 23 06:14:48 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108566098 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.2108566098
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all.2690230653
Short name T160
Test name
Test status
Simulation time 10600890236 ps
CPU time 40.97 seconds
Started Aug 23 06:14:51 AM UTC 24
Finished Aug 23 06:15:34 AM UTC 24
Peak memory 210840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690230653 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all.2690230653
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all_with_rand_reset.3453016666
Short name T165
Test name
Test status
Simulation time 3505885951 ps
CPU time 44.06 seconds
Started Aug 23 06:14:51 AM UTC 24
Finished Aug 23 06:15:37 AM UTC 24
Peak memory 220324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453016666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.3453016666
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/12.clkmgr_trans.1693172203
Short name T277
Test name
Test status
Simulation time 26630061 ps
CPU time 0.8 seconds
Started Aug 23 06:14:49 AM UTC 24
Finished Aug 23 06:14:51 AM UTC 24
Peak memory 209920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693172203 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.1693172203
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/12.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/13.clkmgr_alert_test.3442830136
Short name T296
Test name
Test status
Simulation time 41546584 ps
CPU time 0.73 seconds
Started Aug 23 06:14:58 AM UTC 24
Finished Aug 23 06:14:59 AM UTC 24
Peak memory 208796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442830136 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_alert_test.3442830136
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.329023156
Short name T119
Test name
Test status
Simulation time 26253964 ps
CPU time 0.74 seconds
Started Aug 23 06:14:56 AM UTC 24
Finished Aug 23 06:14:58 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329023156 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_handshake_intersig_mubi.329023156
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_status.3099462140
Short name T288
Test name
Test status
Simulation time 32584537 ps
CPU time 0.66 seconds
Started Aug 23 06:14:54 AM UTC 24
Finished Aug 23 06:14:56 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099462140 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.3099462140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/13.clkmgr_div_intersig_mubi.2925132094
Short name T294
Test name
Test status
Simulation time 26481126 ps
CPU time 0.81 seconds
Started Aug 23 06:14:56 AM UTC 24
Finished Aug 23 06:14:58 AM UTC 24
Peak memory 209968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925132094 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_div_intersig_mubi.2925132094
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/13.clkmgr_extclk.255792992
Short name T285
Test name
Test status
Simulation time 24589246 ps
CPU time 0.8 seconds
Started Aug 23 06:14:52 AM UTC 24
Finished Aug 23 06:14:54 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255792992 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.255792992
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency.1784450958
Short name T180
Test name
Test status
Simulation time 1528204396 ps
CPU time 7.21 seconds
Started Aug 23 06:14:52 AM UTC 24
Finished Aug 23 06:15:01 AM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784450958 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.1784450958
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency_timeout.2091068939
Short name T295
Test name
Test status
Simulation time 985408315 ps
CPU time 5.31 seconds
Started Aug 23 06:14:52 AM UTC 24
Finished Aug 23 06:14:59 AM UTC 24
Peak memory 210568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091068939 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_timeout.2091068939
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/13.clkmgr_idle_intersig_mubi.162803245
Short name T293
Test name
Test status
Simulation time 89787566 ps
CPU time 0.98 seconds
Started Aug 23 06:14:55 AM UTC 24
Finished Aug 23 06:14:57 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162803245 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_idle_intersig_mubi.162803245
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.3180492442
Short name T292
Test name
Test status
Simulation time 75936947 ps
CPU time 0.92 seconds
Started Aug 23 06:14:55 AM UTC 24
Finished Aug 23 06:14:57 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180492442
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_clk_byp_req_intersig_mubi.3180492442
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.4136632894
Short name T291
Test name
Test status
Simulation time 72232708 ps
CPU time 0.86 seconds
Started Aug 23 06:14:55 AM UTC 24
Finished Aug 23 06:14:57 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136632894
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_ctrl_intersig_mubi.4136632894
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/13.clkmgr_peri.3273502732
Short name T287
Test name
Test status
Simulation time 23406471 ps
CPU time 0.71 seconds
Started Aug 23 06:14:54 AM UTC 24
Finished Aug 23 06:14:56 AM UTC 24
Peak memory 209420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273502732 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.3273502732
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/13.clkmgr_regwen.3251909619
Short name T182
Test name
Test status
Simulation time 1194360738 ps
CPU time 4.16 seconds
Started Aug 23 06:14:56 AM UTC 24
Finished Aug 23 06:15:02 AM UTC 24
Peak memory 210568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251909619 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.3251909619
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/13.clkmgr_smoke.3812919079
Short name T284
Test name
Test status
Simulation time 54263482 ps
CPU time 0.85 seconds
Started Aug 23 06:14:51 AM UTC 24
Finished Aug 23 06:14:53 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812919079 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.3812919079
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all_with_rand_reset.2845010841
Short name T83
Test name
Test status
Simulation time 1478702533 ps
CPU time 16.27 seconds
Started Aug 23 06:14:56 AM UTC 24
Finished Aug 23 06:15:14 AM UTC 24
Peak memory 220348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845010841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.2845010841
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/13.clkmgr_trans.77938990
Short name T290
Test name
Test status
Simulation time 41366304 ps
CPU time 0.9 seconds
Started Aug 23 06:14:54 AM UTC 24
Finished Aug 23 06:14:56 AM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77938990 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.77938990
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/13.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/14.clkmgr_alert_test.3965659507
Short name T302
Test name
Test status
Simulation time 18472778 ps
CPU time 0.7 seconds
Started Aug 23 06:15:03 AM UTC 24
Finished Aug 23 06:15:05 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965659507 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_alert_test.3965659507
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.1862747226
Short name T120
Test name
Test status
Simulation time 60209495 ps
CPU time 0.78 seconds
Started Aug 23 06:15:02 AM UTC 24
Finished Aug 23 06:15:03 AM UTC 24
Peak memory 210004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862747226 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_handshake_intersig_mubi.1862747226
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_status.1722078557
Short name T183
Test name
Test status
Simulation time 17480976 ps
CPU time 0.63 seconds
Started Aug 23 06:15:00 AM UTC 24
Finished Aug 23 06:15:02 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722078557 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.1722078557
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/14.clkmgr_div_intersig_mubi.2288032246
Short name T299
Test name
Test status
Simulation time 60498946 ps
CPU time 0.84 seconds
Started Aug 23 06:15:02 AM UTC 24
Finished Aug 23 06:15:03 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288032246 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_div_intersig_mubi.2288032246
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/14.clkmgr_extclk.3962511954
Short name T297
Test name
Test status
Simulation time 35905704 ps
CPU time 0.77 seconds
Started Aug 23 06:14:58 AM UTC 24
Finished Aug 23 06:15:00 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962511954 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.3962511954
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency.3449202510
Short name T315
Test name
Test status
Simulation time 2207068735 ps
CPU time 8.98 seconds
Started Aug 23 06:14:59 AM UTC 24
Finished Aug 23 06:15:09 AM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449202510 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.3449202510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency_timeout.3310552499
Short name T301
Test name
Test status
Simulation time 1035465402 ps
CPU time 4.41 seconds
Started Aug 23 06:14:59 AM UTC 24
Finished Aug 23 06:15:04 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310552499 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_timeout.3310552499
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/14.clkmgr_idle_intersig_mubi.2240348221
Short name T186
Test name
Test status
Simulation time 126180164 ps
CPU time 1.2 seconds
Started Aug 23 06:15:00 AM UTC 24
Finished Aug 23 06:15:03 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240348221 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_idle_intersig_mubi.2240348221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.1576610475
Short name T298
Test name
Test status
Simulation time 34741127 ps
CPU time 0.67 seconds
Started Aug 23 06:15:02 AM UTC 24
Finished Aug 23 06:15:03 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576610475
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_clk_byp_req_intersig_mubi.1576610475
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.735609524
Short name T185
Test name
Test status
Simulation time 94829764 ps
CPU time 0.96 seconds
Started Aug 23 06:15:00 AM UTC 24
Finished Aug 23 06:15:02 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735609524 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_ctrl_intersig_mubi.735609524
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/14.clkmgr_peri.1627760069
Short name T181
Test name
Test status
Simulation time 46096404 ps
CPU time 0.72 seconds
Started Aug 23 06:14:59 AM UTC 24
Finished Aug 23 06:15:01 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627760069 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.1627760069
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/14.clkmgr_regwen.3026376180
Short name T304
Test name
Test status
Simulation time 386313509 ps
CPU time 2.3 seconds
Started Aug 23 06:15:02 AM UTC 24
Finished Aug 23 06:15:05 AM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026376180 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.3026376180
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/14.clkmgr_smoke.512962844
Short name T158
Test name
Test status
Simulation time 22923735 ps
CPU time 0.8 seconds
Started Aug 23 06:14:58 AM UTC 24
Finished Aug 23 06:15:00 AM UTC 24
Peak memory 208444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512962844 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.512962844
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/14.clkmgr_stress_all.2834090282
Short name T161
Test name
Test status
Simulation time 5663350220 ps
CPU time 30.17 seconds
Started Aug 23 06:15:03 AM UTC 24
Finished Aug 23 06:15:34 AM UTC 24
Peak memory 210740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834090282 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all.2834090282
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/14.clkmgr_stress_all_with_rand_reset.2934794694
Short name T167
Test name
Test status
Simulation time 9556141796 ps
CPU time 42.45 seconds
Started Aug 23 06:15:03 AM UTC 24
Finished Aug 23 06:15:47 AM UTC 24
Peak memory 220480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934794694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.2934794694
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/14.clkmgr_trans.367902230
Short name T184
Test name
Test status
Simulation time 43615261 ps
CPU time 0.74 seconds
Started Aug 23 06:15:00 AM UTC 24
Finished Aug 23 06:15:02 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367902230 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.367902230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/14.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/15.clkmgr_alert_test.1839936084
Short name T314
Test name
Test status
Simulation time 17760714 ps
CPU time 0.64 seconds
Started Aug 23 06:15:07 AM UTC 24
Finished Aug 23 06:15:09 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839936084 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_alert_test.1839936084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.3578822601
Short name T310
Test name
Test status
Simulation time 35172745 ps
CPU time 0.79 seconds
Started Aug 23 06:15:06 AM UTC 24
Finished Aug 23 06:15:08 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578822601 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_handshake_intersig_mubi.3578822601
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_status.827237737
Short name T307
Test name
Test status
Simulation time 18632723 ps
CPU time 0.65 seconds
Started Aug 23 06:15:04 AM UTC 24
Finished Aug 23 06:15:06 AM UTC 24
Peak memory 209132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827237737 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.827237737
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/15.clkmgr_div_intersig_mubi.2837021798
Short name T312
Test name
Test status
Simulation time 65308566 ps
CPU time 0.83 seconds
Started Aug 23 06:15:06 AM UTC 24
Finished Aug 23 06:15:08 AM UTC 24
Peak memory 209004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837021798 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_div_intersig_mubi.2837021798
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/15.clkmgr_extclk.2847430244
Short name T305
Test name
Test status
Simulation time 126228984 ps
CPU time 1.07 seconds
Started Aug 23 06:15:03 AM UTC 24
Finished Aug 23 06:15:05 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847430244 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.2847430244
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency.2019965697
Short name T318
Test name
Test status
Simulation time 1440262593 ps
CPU time 5.84 seconds
Started Aug 23 06:15:03 AM UTC 24
Finished Aug 23 06:15:10 AM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019965697 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.2019965697
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency_timeout.2626876796
Short name T338
Test name
Test status
Simulation time 1461710861 ps
CPU time 10.93 seconds
Started Aug 23 06:15:04 AM UTC 24
Finished Aug 23 06:15:16 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626876796 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_timeout.2626876796
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/15.clkmgr_idle_intersig_mubi.3508509502
Short name T313
Test name
Test status
Simulation time 145666285 ps
CPU time 1.1 seconds
Started Aug 23 06:15:06 AM UTC 24
Finished Aug 23 06:15:08 AM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508509502 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_idle_intersig_mubi.3508509502
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.2499598166
Short name T311
Test name
Test status
Simulation time 42974124 ps
CPU time 0.84 seconds
Started Aug 23 06:15:06 AM UTC 24
Finished Aug 23 06:15:08 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499598166
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_lc_clk_byp_req_intersig_mubi.2499598166
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.4118761506
Short name T309
Test name
Test status
Simulation time 16295133 ps
CPU time 0.68 seconds
Started Aug 23 06:15:06 AM UTC 24
Finished Aug 23 06:15:07 AM UTC 24
Peak memory 208968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118761506
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_lc_ctrl_intersig_mubi.4118761506
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/15.clkmgr_peri.104950858
Short name T306
Test name
Test status
Simulation time 17476785 ps
CPU time 0.62 seconds
Started Aug 23 06:15:04 AM UTC 24
Finished Aug 23 06:15:06 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104950858 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.104950858
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/15.clkmgr_regwen.2019566328
Short name T317
Test name
Test status
Simulation time 562664432 ps
CPU time 2.25 seconds
Started Aug 23 06:15:06 AM UTC 24
Finished Aug 23 06:15:09 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019566328 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.2019566328
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/15.clkmgr_smoke.2571040592
Short name T303
Test name
Test status
Simulation time 39483363 ps
CPU time 0.79 seconds
Started Aug 23 06:15:03 AM UTC 24
Finished Aug 23 06:15:05 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571040592 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.2571040592
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all.78386870
Short name T425
Test name
Test status
Simulation time 10080789420 ps
CPU time 40.93 seconds
Started Aug 23 06:15:07 AM UTC 24
Finished Aug 23 06:15:49 AM UTC 24
Peak memory 211036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78386870 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all.78386870
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all_with_rand_reset.2504889632
Short name T449
Test name
Test status
Simulation time 5815573942 ps
CPU time 49.11 seconds
Started Aug 23 06:15:07 AM UTC 24
Finished Aug 23 06:15:58 AM UTC 24
Peak memory 220324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504889632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.2504889632
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/15.clkmgr_trans.3121514060
Short name T308
Test name
Test status
Simulation time 23718677 ps
CPU time 0.74 seconds
Started Aug 23 06:15:04 AM UTC 24
Finished Aug 23 06:15:06 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121514060 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.3121514060
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/15.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/16.clkmgr_alert_test.769754817
Short name T331
Test name
Test status
Simulation time 45886965 ps
CPU time 0.83 seconds
Started Aug 23 06:15:12 AM UTC 24
Finished Aug 23 06:15:14 AM UTC 24
Peak memory 210024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769754817 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_alert_test.769754817
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.3589270813
Short name T329
Test name
Test status
Simulation time 159602634 ps
CPU time 1.17 seconds
Started Aug 23 06:15:10 AM UTC 24
Finished Aug 23 06:15:13 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589270813 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_handshake_intersig_mubi.3589270813
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_status.507134634
Short name T323
Test name
Test status
Simulation time 16699048 ps
CPU time 0.61 seconds
Started Aug 23 06:15:10 AM UTC 24
Finished Aug 23 06:15:12 AM UTC 24
Peak memory 209132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507134634 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.507134634
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/16.clkmgr_div_intersig_mubi.1067682532
Short name T327
Test name
Test status
Simulation time 27289382 ps
CPU time 0.81 seconds
Started Aug 23 06:15:10 AM UTC 24
Finished Aug 23 06:15:12 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067682532 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_div_intersig_mubi.1067682532
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/16.clkmgr_extclk.2754542016
Short name T322
Test name
Test status
Simulation time 285150745 ps
CPU time 1.42 seconds
Started Aug 23 06:15:09 AM UTC 24
Finished Aug 23 06:15:11 AM UTC 24
Peak memory 209584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754542016 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.2754542016
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/16.clkmgr_frequency.3572285257
Short name T352
Test name
Test status
Simulation time 2131271397 ps
CPU time 11.66 seconds
Started Aug 23 06:15:09 AM UTC 24
Finished Aug 23 06:15:21 AM UTC 24
Peak memory 210900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572285257 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.3572285257
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/16.clkmgr_frequency_timeout.356886968
Short name T328
Test name
Test status
Simulation time 633444675 ps
CPU time 2.72 seconds
Started Aug 23 06:15:09 AM UTC 24
Finished Aug 23 06:15:12 AM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356886968 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_timeout.356886968
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/16.clkmgr_idle_intersig_mubi.2804621945
Short name T326
Test name
Test status
Simulation time 38216912 ps
CPU time 0.9 seconds
Started Aug 23 06:15:10 AM UTC 24
Finished Aug 23 06:15:12 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804621945 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_idle_intersig_mubi.2804621945
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.4010454332
Short name T325
Test name
Test status
Simulation time 43419867 ps
CPU time 0.8 seconds
Started Aug 23 06:15:10 AM UTC 24
Finished Aug 23 06:15:12 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010454332
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_lc_clk_byp_req_intersig_mubi.4010454332
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.3427348959
Short name T324
Test name
Test status
Simulation time 50485057 ps
CPU time 0.72 seconds
Started Aug 23 06:15:10 AM UTC 24
Finished Aug 23 06:15:12 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427348959
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_lc_ctrl_intersig_mubi.3427348959
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/16.clkmgr_peri.3459952752
Short name T321
Test name
Test status
Simulation time 52919976 ps
CPU time 0.72 seconds
Started Aug 23 06:15:09 AM UTC 24
Finished Aug 23 06:15:10 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459952752 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.3459952752
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/16.clkmgr_regwen.4007501291
Short name T164
Test name
Test status
Simulation time 956156768 ps
CPU time 3.46 seconds
Started Aug 23 06:15:12 AM UTC 24
Finished Aug 23 06:15:16 AM UTC 24
Peak memory 210568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007501291 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.4007501291
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/16.clkmgr_smoke.2701161037
Short name T320
Test name
Test status
Simulation time 23953627 ps
CPU time 0.76 seconds
Started Aug 23 06:15:09 AM UTC 24
Finished Aug 23 06:15:10 AM UTC 24
Peak memory 209472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701161037 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.2701161037
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all.1571186225
Short name T378
Test name
Test status
Simulation time 5914495234 ps
CPU time 18.74 seconds
Started Aug 23 06:15:12 AM UTC 24
Finished Aug 23 06:15:32 AM UTC 24
Peak memory 210744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571186225 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all.1571186225
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/16.clkmgr_trans.1390811926
Short name T319
Test name
Test status
Simulation time 14296567 ps
CPU time 0.65 seconds
Started Aug 23 06:15:09 AM UTC 24
Finished Aug 23 06:15:10 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390811926 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.1390811926
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/16.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/17.clkmgr_alert_test.2449531221
Short name T341
Test name
Test status
Simulation time 43388173 ps
CPU time 0.72 seconds
Started Aug 23 06:15:16 AM UTC 24
Finished Aug 23 06:15:18 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449531221 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_alert_test.2449531221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.1096143570
Short name T121
Test name
Test status
Simulation time 43421691 ps
CPU time 0.85 seconds
Started Aug 23 06:15:15 AM UTC 24
Finished Aug 23 06:15:16 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096143570 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_handshake_intersig_mubi.1096143570
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/17.clkmgr_clk_status.3882071507
Short name T333
Test name
Test status
Simulation time 39986609 ps
CPU time 0.69 seconds
Started Aug 23 06:15:13 AM UTC 24
Finished Aug 23 06:15:15 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882071507 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.3882071507
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/17.clkmgr_div_intersig_mubi.3701685109
Short name T343
Test name
Test status
Simulation time 98824683 ps
CPU time 1.08 seconds
Started Aug 23 06:15:16 AM UTC 24
Finished Aug 23 06:15:18 AM UTC 24
Peak memory 209004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701685109 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_div_intersig_mubi.3701685109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/17.clkmgr_extclk.3401428615
Short name T335
Test name
Test status
Simulation time 83219859 ps
CPU time 0.97 seconds
Started Aug 23 06:15:13 AM UTC 24
Finished Aug 23 06:15:15 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401428615 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.3401428615
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/17.clkmgr_frequency.1600080364
Short name T337
Test name
Test status
Simulation time 214915526 ps
CPU time 1.45 seconds
Started Aug 23 06:15:13 AM UTC 24
Finished Aug 23 06:15:16 AM UTC 24
Peak memory 209932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600080364 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.1600080364
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/17.clkmgr_frequency_timeout.3199222018
Short name T364
Test name
Test status
Simulation time 2424654636 ps
CPU time 11.89 seconds
Started Aug 23 06:15:13 AM UTC 24
Finished Aug 23 06:15:26 AM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199222018 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_timeout.3199222018
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/17.clkmgr_idle_intersig_mubi.3347509547
Short name T336
Test name
Test status
Simulation time 48229249 ps
CPU time 0.86 seconds
Started Aug 23 06:15:13 AM UTC 24
Finished Aug 23 06:15:15 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347509547 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_idle_intersig_mubi.3347509547
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.3973311683
Short name T339
Test name
Test status
Simulation time 20709424 ps
CPU time 0.78 seconds
Started Aug 23 06:15:15 AM UTC 24
Finished Aug 23 06:15:16 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973311683
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_clk_byp_req_intersig_mubi.3973311683
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.4083738996
Short name T340
Test name
Test status
Simulation time 37956110 ps
CPU time 0.83 seconds
Started Aug 23 06:15:15 AM UTC 24
Finished Aug 23 06:15:16 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083738996
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_ctrl_intersig_mubi.4083738996
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/17.clkmgr_peri.1154559036
Short name T332
Test name
Test status
Simulation time 54297596 ps
CPU time 0.73 seconds
Started Aug 23 06:15:13 AM UTC 24
Finished Aug 23 06:15:15 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154559036 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.1154559036
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/17.clkmgr_regwen.927284352
Short name T342
Test name
Test status
Simulation time 92554278 ps
CPU time 0.88 seconds
Started Aug 23 06:15:16 AM UTC 24
Finished Aug 23 06:15:18 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927284352 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.927284352
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/17.clkmgr_smoke.2402736848
Short name T330
Test name
Test status
Simulation time 16923377 ps
CPU time 0.71 seconds
Started Aug 23 06:15:12 AM UTC 24
Finished Aug 23 06:15:13 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402736848 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.2402736848
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/17.clkmgr_stress_all.2265736367
Short name T377
Test name
Test status
Simulation time 3622438675 ps
CPU time 14.44 seconds
Started Aug 23 06:15:16 AM UTC 24
Finished Aug 23 06:15:32 AM UTC 24
Peak memory 210868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265736367 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all.2265736367
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/17.clkmgr_stress_all_with_rand_reset.3561589969
Short name T168
Test name
Test status
Simulation time 3590602970 ps
CPU time 48.96 seconds
Started Aug 23 06:15:16 AM UTC 24
Finished Aug 23 06:16:06 AM UTC 24
Peak memory 220320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561589969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.3561589969
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/17.clkmgr_trans.4025673376
Short name T334
Test name
Test status
Simulation time 25711795 ps
CPU time 0.68 seconds
Started Aug 23 06:15:13 AM UTC 24
Finished Aug 23 06:15:15 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025673376 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.4025673376
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/17.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/18.clkmgr_alert_test.3393294258
Short name T355
Test name
Test status
Simulation time 86972196 ps
CPU time 0.89 seconds
Started Aug 23 06:15:22 AM UTC 24
Finished Aug 23 06:15:24 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393294258 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_alert_test.3393294258
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.1029946386
Short name T354
Test name
Test status
Simulation time 51066572 ps
CPU time 0.96 seconds
Started Aug 23 06:15:20 AM UTC 24
Finished Aug 23 06:15:22 AM UTC 24
Peak memory 208084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029946386 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_handshake_intersig_mubi.1029946386
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/18.clkmgr_clk_status.3789012189
Short name T348
Test name
Test status
Simulation time 15821694 ps
CPU time 0.63 seconds
Started Aug 23 06:15:19 AM UTC 24
Finished Aug 23 06:15:20 AM UTC 24
Peak memory 209736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789012189 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.3789012189
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/18.clkmgr_div_intersig_mubi.1266894209
Short name T353
Test name
Test status
Simulation time 34403691 ps
CPU time 0.81 seconds
Started Aug 23 06:15:20 AM UTC 24
Finished Aug 23 06:15:22 AM UTC 24
Peak memory 208024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266894209 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_div_intersig_mubi.1266894209
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/18.clkmgr_extclk.145562592
Short name T344
Test name
Test status
Simulation time 20480697 ps
CPU time 0.73 seconds
Started Aug 23 06:15:17 AM UTC 24
Finished Aug 23 06:15:19 AM UTC 24
Peak memory 210068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145562592 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.145562592
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/18.clkmgr_frequency.3198880557
Short name T373
Test name
Test status
Simulation time 1517868387 ps
CPU time 11.33 seconds
Started Aug 23 06:15:18 AM UTC 24
Finished Aug 23 06:15:30 AM UTC 24
Peak memory 210428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198880557 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.3198880557
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/18.clkmgr_frequency_timeout.2126645846
Short name T382
Test name
Test status
Simulation time 1815768455 ps
CPU time 13.35 seconds
Started Aug 23 06:15:18 AM UTC 24
Finished Aug 23 06:15:32 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126645846 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_timeout.2126645846
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/18.clkmgr_idle_intersig_mubi.1122496083
Short name T351
Test name
Test status
Simulation time 93027879 ps
CPU time 0.99 seconds
Started Aug 23 06:15:19 AM UTC 24
Finished Aug 23 06:15:21 AM UTC 24
Peak memory 209852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122496083 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_idle_intersig_mubi.1122496083
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.2012893368
Short name T349
Test name
Test status
Simulation time 51504505 ps
CPU time 0.76 seconds
Started Aug 23 06:15:19 AM UTC 24
Finished Aug 23 06:15:21 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012893368
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_clk_byp_req_intersig_mubi.2012893368
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.3219220244
Short name T350
Test name
Test status
Simulation time 76080864 ps
CPU time 0.79 seconds
Started Aug 23 06:15:19 AM UTC 24
Finished Aug 23 06:15:21 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219220244
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_ctrl_intersig_mubi.3219220244
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/18.clkmgr_peri.396750951
Short name T346
Test name
Test status
Simulation time 19886548 ps
CPU time 0.71 seconds
Started Aug 23 06:15:18 AM UTC 24
Finished Aug 23 06:15:19 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396750951 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.396750951
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/18.clkmgr_regwen.3218303421
Short name T365
Test name
Test status
Simulation time 1067936670 ps
CPU time 5.44 seconds
Started Aug 23 06:15:20 AM UTC 24
Finished Aug 23 06:15:27 AM UTC 24
Peak memory 210568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218303421 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.3218303421
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/18.clkmgr_smoke.3467175194
Short name T345
Test name
Test status
Simulation time 20487724 ps
CPU time 0.77 seconds
Started Aug 23 06:15:17 AM UTC 24
Finished Aug 23 06:15:19 AM UTC 24
Peak memory 210004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467175194 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.3467175194
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/18.clkmgr_stress_all.3921214697
Short name T584
Test name
Test status
Simulation time 11230229694 ps
CPU time 82.88 seconds
Started Aug 23 06:15:22 AM UTC 24
Finished Aug 23 06:16:46 AM UTC 24
Peak memory 210740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921214697 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all.3921214697
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/18.clkmgr_stress_all_with_rand_reset.2206503921
Short name T463
Test name
Test status
Simulation time 6882278707 ps
CPU time 40.76 seconds
Started Aug 23 06:15:20 AM UTC 24
Finished Aug 23 06:16:02 AM UTC 24
Peak memory 227588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206503921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.2206503921
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/18.clkmgr_trans.1097669881
Short name T347
Test name
Test status
Simulation time 22803255 ps
CPU time 0.82 seconds
Started Aug 23 06:15:18 AM UTC 24
Finished Aug 23 06:15:19 AM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097669881 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.1097669881
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/18.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/19.clkmgr_alert_test.756193821
Short name T370
Test name
Test status
Simulation time 18703202 ps
CPU time 0.62 seconds
Started Aug 23 06:15:27 AM UTC 24
Finished Aug 23 06:15:29 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756193821 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_alert_test.756193821
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.3063349087
Short name T367
Test name
Test status
Simulation time 14798852 ps
CPU time 0.66 seconds
Started Aug 23 06:15:26 AM UTC 24
Finished Aug 23 06:15:27 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063349087 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_handshake_intersig_mubi.3063349087
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/19.clkmgr_clk_status.1835412025
Short name T358
Test name
Test status
Simulation time 17089786 ps
CPU time 0.63 seconds
Started Aug 23 06:15:23 AM UTC 24
Finished Aug 23 06:15:25 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835412025 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.1835412025
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/19.clkmgr_div_intersig_mubi.3374925362
Short name T368
Test name
Test status
Simulation time 280945764 ps
CPU time 1.45 seconds
Started Aug 23 06:15:26 AM UTC 24
Finished Aug 23 06:15:28 AM UTC 24
Peak memory 210448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374925362 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_div_intersig_mubi.3374925362
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/19.clkmgr_extclk.4177464174
Short name T356
Test name
Test status
Simulation time 88459003 ps
CPU time 0.9 seconds
Started Aug 23 06:15:22 AM UTC 24
Finished Aug 23 06:15:24 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177464174 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.4177464174
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/19.clkmgr_frequency.313362541
Short name T357
Test name
Test status
Simulation time 368142457 ps
CPU time 1.83 seconds
Started Aug 23 06:15:22 AM UTC 24
Finished Aug 23 06:15:25 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313362541 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.313362541
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/19.clkmgr_frequency_timeout.903160656
Short name T362
Test name
Test status
Simulation time 402759490 ps
CPU time 2.09 seconds
Started Aug 23 06:15:23 AM UTC 24
Finished Aug 23 06:15:26 AM UTC 24
Peak memory 210344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903160656 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_timeout.903160656
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/19.clkmgr_idle_intersig_mubi.1555682715
Short name T366
Test name
Test status
Simulation time 292631664 ps
CPU time 1.46 seconds
Started Aug 23 06:15:24 AM UTC 24
Finished Aug 23 06:15:27 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555682715 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_idle_intersig_mubi.1555682715
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.2444878539
Short name T363
Test name
Test status
Simulation time 53159321 ps
CPU time 0.8 seconds
Started Aug 23 06:15:24 AM UTC 24
Finished Aug 23 06:15:26 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444878539
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_lc_clk_byp_req_intersig_mubi.2444878539
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.3342187236
Short name T361
Test name
Test status
Simulation time 15905075 ps
CPU time 0.71 seconds
Started Aug 23 06:15:24 AM UTC 24
Finished Aug 23 06:15:26 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342187236
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_lc_ctrl_intersig_mubi.3342187236
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/19.clkmgr_peri.3001188649
Short name T359
Test name
Test status
Simulation time 45104450 ps
CPU time 0.71 seconds
Started Aug 23 06:15:23 AM UTC 24
Finished Aug 23 06:15:25 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001188649 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.3001188649
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/19.clkmgr_regwen.2104767949
Short name T369
Test name
Test status
Simulation time 319628877 ps
CPU time 1.66 seconds
Started Aug 23 06:15:26 AM UTC 24
Finished Aug 23 06:15:28 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104767949 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.2104767949
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/19.clkmgr_smoke.2290649550
Short name T159
Test name
Test status
Simulation time 64762120 ps
CPU time 0.87 seconds
Started Aug 23 06:15:22 AM UTC 24
Finished Aug 23 06:15:24 AM UTC 24
Peak memory 209972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290649550 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.2290649550
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all.1179102472
Short name T486
Test name
Test status
Simulation time 9089099256 ps
CPU time 42.54 seconds
Started Aug 23 06:15:27 AM UTC 24
Finished Aug 23 06:16:11 AM UTC 24
Peak memory 210448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179102472 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all.1179102472
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all_with_rand_reset.3745315227
Short name T199
Test name
Test status
Simulation time 1209424337 ps
CPU time 19.01 seconds
Started Aug 23 06:15:27 AM UTC 24
Finished Aug 23 06:15:47 AM UTC 24
Peak memory 226760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745315227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.3745315227
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/19.clkmgr_trans.3960519384
Short name T360
Test name
Test status
Simulation time 304383595 ps
CPU time 1.48 seconds
Started Aug 23 06:15:23 AM UTC 24
Finished Aug 23 06:15:26 AM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960519384 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.3960519384
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/19.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_alert_test.311709746
Short name T46
Test name
Test status
Simulation time 14920268 ps
CPU time 0.66 seconds
Started Aug 23 06:13:45 AM UTC 24
Finished Aug 23 06:13:47 AM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311709746 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_alert_test.311709746
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.1082790782
Short name T42
Test name
Test status
Simulation time 12860529 ps
CPU time 0.67 seconds
Started Aug 23 06:13:43 AM UTC 24
Finished Aug 23 06:13:45 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082790782 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_handshake_intersig_mubi.1082790782
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_status.1599519505
Short name T25
Test name
Test status
Simulation time 54485732 ps
CPU time 0.72 seconds
Started Aug 23 06:13:41 AM UTC 24
Finished Aug 23 06:13:43 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599519505 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.1599519505
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_extclk.1249422883
Short name T23
Test name
Test status
Simulation time 42907595 ps
CPU time 0.83 seconds
Started Aug 23 06:13:39 AM UTC 24
Finished Aug 23 06:13:41 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249422883 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.1249422883
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency.4289805653
Short name T9
Test name
Test status
Simulation time 685273770 ps
CPU time 4.17 seconds
Started Aug 23 06:13:39 AM UTC 24
Finished Aug 23 06:13:44 AM UTC 24
Peak memory 210624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289805653 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.4289805653
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency_timeout.1433634553
Short name T58
Test name
Test status
Simulation time 1701543408 ps
CPU time 11.96 seconds
Started Aug 23 06:13:40 AM UTC 24
Finished Aug 23 06:13:53 AM UTC 24
Peak memory 210464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433634553 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_timeout.1433634553
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_idle_intersig_mubi.1268736224
Short name T93
Test name
Test status
Simulation time 47397481 ps
CPU time 0.84 seconds
Started Aug 23 06:13:41 AM UTC 24
Finished Aug 23 06:13:43 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268736224 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_idle_intersig_mubi.1268736224
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.1621774223
Short name T43
Test name
Test status
Simulation time 17995843 ps
CPU time 0.68 seconds
Started Aug 23 06:13:43 AM UTC 24
Finished Aug 23 06:13:45 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621774223
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_lc_clk_byp_req_intersig_mubi.1621774223
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.2184882908
Short name T27
Test name
Test status
Simulation time 45058707 ps
CPU time 0.77 seconds
Started Aug 23 06:13:41 AM UTC 24
Finished Aug 23 06:13:43 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184882908
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_lc_ctrl_intersig_mubi.2184882908
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_peri.4028421916
Short name T24
Test name
Test status
Simulation time 16606469 ps
CPU time 0.67 seconds
Started Aug 23 06:13:41 AM UTC 24
Finished Aug 23 06:13:43 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028421916 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.4028421916
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_sec_cm.1553603477
Short name T45
Test name
Test status
Simulation time 341530445 ps
CPU time 2.22 seconds
Started Aug 23 06:13:43 AM UTC 24
Finished Aug 23 06:13:46 AM UTC 24
Peak memory 242608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553603477 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_sec_cm.1553603477
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_smoke.3772267713
Short name T22
Test name
Test status
Simulation time 41935682 ps
CPU time 0.77 seconds
Started Aug 23 06:13:39 AM UTC 24
Finished Aug 23 06:13:40 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772267713 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.3772267713
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all.2271672403
Short name T108
Test name
Test status
Simulation time 7213975990 ps
CPU time 36.27 seconds
Started Aug 23 06:13:44 AM UTC 24
Finished Aug 23 06:14:22 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271672403 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all.2271672403
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/2.clkmgr_trans.2065870385
Short name T26
Test name
Test status
Simulation time 36389578 ps
CPU time 0.79 seconds
Started Aug 23 06:13:41 AM UTC 24
Finished Aug 23 06:13:43 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065870385 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.2065870385
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/2.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/20.clkmgr_alert_test.2953970236
Short name T385
Test name
Test status
Simulation time 37583337 ps
CPU time 0.69 seconds
Started Aug 23 06:15:33 AM UTC 24
Finished Aug 23 06:15:34 AM UTC 24
Peak memory 209268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953970236 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_alert_test.2953970236
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.3628713733
Short name T122
Test name
Test status
Simulation time 42890401 ps
CPU time 0.76 seconds
Started Aug 23 06:15:31 AM UTC 24
Finished Aug 23 06:15:33 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628713733 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_handshake_intersig_mubi.3628713733
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/20.clkmgr_clk_status.1807869332
Short name T375
Test name
Test status
Simulation time 18866851 ps
CPU time 0.68 seconds
Started Aug 23 06:15:30 AM UTC 24
Finished Aug 23 06:15:32 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807869332 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.1807869332
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/20.clkmgr_div_intersig_mubi.2783228680
Short name T384
Test name
Test status
Simulation time 48020767 ps
CPU time 0.84 seconds
Started Aug 23 06:15:31 AM UTC 24
Finished Aug 23 06:15:33 AM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783228680 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_div_intersig_mubi.2783228680
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/20.clkmgr_extclk.1262923794
Short name T372
Test name
Test status
Simulation time 39359756 ps
CPU time 0.78 seconds
Started Aug 23 06:15:27 AM UTC 24
Finished Aug 23 06:15:29 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262923794 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.1262923794
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/20.clkmgr_frequency.802364649
Short name T395
Test name
Test status
Simulation time 2840135448 ps
CPU time 9.69 seconds
Started Aug 23 06:15:28 AM UTC 24
Finished Aug 23 06:15:39 AM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802364649 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.802364649
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/20.clkmgr_frequency_timeout.2559498733
Short name T383
Test name
Test status
Simulation time 503297512 ps
CPU time 2.76 seconds
Started Aug 23 06:15:28 AM UTC 24
Finished Aug 23 06:15:32 AM UTC 24
Peak memory 210388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559498733 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_timeout.2559498733
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/20.clkmgr_idle_intersig_mubi.1058923707
Short name T381
Test name
Test status
Simulation time 105576299 ps
CPU time 1 seconds
Started Aug 23 06:15:30 AM UTC 24
Finished Aug 23 06:15:32 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058923707 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_idle_intersig_mubi.1058923707
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.3518690806
Short name T379
Test name
Test status
Simulation time 16013837 ps
CPU time 0.66 seconds
Started Aug 23 06:15:30 AM UTC 24
Finished Aug 23 06:15:32 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518690806
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_lc_clk_byp_req_intersig_mubi.3518690806
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.1480084105
Short name T380
Test name
Test status
Simulation time 32649526 ps
CPU time 0.78 seconds
Started Aug 23 06:15:30 AM UTC 24
Finished Aug 23 06:15:32 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480084105
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_lc_ctrl_intersig_mubi.1480084105
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/20.clkmgr_peri.1479283535
Short name T374
Test name
Test status
Simulation time 16172199 ps
CPU time 0.65 seconds
Started Aug 23 06:15:28 AM UTC 24
Finished Aug 23 06:15:30 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479283535 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.1479283535
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/20.clkmgr_smoke.540203489
Short name T371
Test name
Test status
Simulation time 33214181 ps
CPU time 0.79 seconds
Started Aug 23 06:15:27 AM UTC 24
Finished Aug 23 06:15:29 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540203489 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.540203489
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/20.clkmgr_stress_all.3506797924
Short name T455
Test name
Test status
Simulation time 5215722395 ps
CPU time 25.69 seconds
Started Aug 23 06:15:33 AM UTC 24
Finished Aug 23 06:15:59 AM UTC 24
Peak memory 210808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506797924 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all.3506797924
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/20.clkmgr_stress_all_with_rand_reset.746714436
Short name T176
Test name
Test status
Simulation time 11184982572 ps
CPU time 65.64 seconds
Started Aug 23 06:15:32 AM UTC 24
Finished Aug 23 06:16:40 AM UTC 24
Peak memory 220288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746714436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.746714436
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/20.clkmgr_trans.4013021160
Short name T376
Test name
Test status
Simulation time 45597400 ps
CPU time 0.79 seconds
Started Aug 23 06:15:30 AM UTC 24
Finished Aug 23 06:15:32 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013021160 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.4013021160
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/20.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/21.clkmgr_alert_test.2123669254
Short name T398
Test name
Test status
Simulation time 73017681 ps
CPU time 0.83 seconds
Started Aug 23 06:15:38 AM UTC 24
Finished Aug 23 06:15:40 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123669254 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_alert_test.2123669254
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.707774848
Short name T123
Test name
Test status
Simulation time 65006569 ps
CPU time 0.89 seconds
Started Aug 23 06:15:35 AM UTC 24
Finished Aug 23 06:15:37 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707774848 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_handshake_intersig_mubi.707774848
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/21.clkmgr_clk_status.2433335747
Short name T389
Test name
Test status
Simulation time 19867929 ps
CPU time 0.64 seconds
Started Aug 23 06:15:34 AM UTC 24
Finished Aug 23 06:15:36 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433335747 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.2433335747
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/21.clkmgr_div_intersig_mubi.126504041
Short name T392
Test name
Test status
Simulation time 25010104 ps
CPU time 0.7 seconds
Started Aug 23 06:15:35 AM UTC 24
Finished Aug 23 06:15:37 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126504041 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_div_intersig_mubi.126504041
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/21.clkmgr_extclk.3832319211
Short name T386
Test name
Test status
Simulation time 17713174 ps
CPU time 0.75 seconds
Started Aug 23 06:15:33 AM UTC 24
Finished Aug 23 06:15:34 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832319211 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.3832319211
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/21.clkmgr_frequency.92296537
Short name T418
Test name
Test status
Simulation time 1760195969 ps
CPU time 13.65 seconds
Started Aug 23 06:15:33 AM UTC 24
Finished Aug 23 06:15:47 AM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92296537 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.92296537
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/21.clkmgr_frequency_timeout.822408298
Short name T404
Test name
Test status
Simulation time 2068835802 ps
CPU time 6.47 seconds
Started Aug 23 06:15:34 AM UTC 24
Finished Aug 23 06:15:41 AM UTC 24
Peak memory 210592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822408298 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_timeout.822408298
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/21.clkmgr_idle_intersig_mubi.4181746727
Short name T391
Test name
Test status
Simulation time 16183938 ps
CPU time 0.74 seconds
Started Aug 23 06:15:35 AM UTC 24
Finished Aug 23 06:15:37 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181746727 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_idle_intersig_mubi.4181746727
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.3964033077
Short name T393
Test name
Test status
Simulation time 25216168 ps
CPU time 0.77 seconds
Started Aug 23 06:15:35 AM UTC 24
Finished Aug 23 06:15:37 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964033077
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_lc_clk_byp_req_intersig_mubi.3964033077
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.2229985145
Short name T394
Test name
Test status
Simulation time 33846167 ps
CPU time 0.85 seconds
Started Aug 23 06:15:35 AM UTC 24
Finished Aug 23 06:15:37 AM UTC 24
Peak memory 209004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229985145
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_lc_ctrl_intersig_mubi.2229985145
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/21.clkmgr_peri.449620173
Short name T388
Test name
Test status
Simulation time 27231165 ps
CPU time 0.7 seconds
Started Aug 23 06:15:34 AM UTC 24
Finished Aug 23 06:15:36 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449620173 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.449620173
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/21.clkmgr_regwen.1179718457
Short name T397
Test name
Test status
Simulation time 448678404 ps
CPU time 1.95 seconds
Started Aug 23 06:15:37 AM UTC 24
Finished Aug 23 06:15:40 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179718457 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.1179718457
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/21.clkmgr_smoke.2394994613
Short name T387
Test name
Test status
Simulation time 25791536 ps
CPU time 0.77 seconds
Started Aug 23 06:15:33 AM UTC 24
Finished Aug 23 06:15:34 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394994613 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.2394994613
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all.2761157599
Short name T453
Test name
Test status
Simulation time 4702677309 ps
CPU time 21.36 seconds
Started Aug 23 06:15:37 AM UTC 24
Finished Aug 23 06:15:59 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761157599 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all.2761157599
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all_with_rand_reset.1153525945
Short name T201
Test name
Test status
Simulation time 500455511 ps
CPU time 5.2 seconds
Started Aug 23 06:15:37 AM UTC 24
Finished Aug 23 06:15:43 AM UTC 24
Peak memory 220060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153525945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.1153525945
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/21.clkmgr_trans.2211228794
Short name T390
Test name
Test status
Simulation time 51063193 ps
CPU time 0.79 seconds
Started Aug 23 06:15:34 AM UTC 24
Finished Aug 23 06:15:36 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211228794 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.2211228794
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/21.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/22.clkmgr_alert_test.3187006588
Short name T410
Test name
Test status
Simulation time 34596133 ps
CPU time 0.69 seconds
Started Aug 23 06:15:42 AM UTC 24
Finished Aug 23 06:15:44 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187006588 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_alert_test.3187006588
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.423520665
Short name T124
Test name
Test status
Simulation time 21519522 ps
CPU time 0.74 seconds
Started Aug 23 06:15:41 AM UTC 24
Finished Aug 23 06:15:43 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423520665 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_handshake_intersig_mubi.423520665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/22.clkmgr_clk_status.1654944410
Short name T403
Test name
Test status
Simulation time 17807561 ps
CPU time 0.68 seconds
Started Aug 23 06:15:39 AM UTC 24
Finished Aug 23 06:15:41 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654944410 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.1654944410
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/22.clkmgr_div_intersig_mubi.3821286755
Short name T405
Test name
Test status
Simulation time 21449342 ps
CPU time 0.64 seconds
Started Aug 23 06:15:41 AM UTC 24
Finished Aug 23 06:15:43 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821286755 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_div_intersig_mubi.3821286755
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/22.clkmgr_extclk.2922105237
Short name T401
Test name
Test status
Simulation time 37918768 ps
CPU time 0.84 seconds
Started Aug 23 06:15:38 AM UTC 24
Finished Aug 23 06:15:40 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922105237 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.2922105237
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/22.clkmgr_frequency.932769225
Short name T441
Test name
Test status
Simulation time 2240613285 ps
CPU time 17.17 seconds
Started Aug 23 06:15:38 AM UTC 24
Finished Aug 23 06:15:57 AM UTC 24
Peak memory 210772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932769225 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.932769225
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/22.clkmgr_frequency_timeout.1334950968
Short name T439
Test name
Test status
Simulation time 2419553609 ps
CPU time 15.92 seconds
Started Aug 23 06:15:38 AM UTC 24
Finished Aug 23 06:15:55 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334950968 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_timeout.1334950968
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/22.clkmgr_idle_intersig_mubi.3664052321
Short name T408
Test name
Test status
Simulation time 96558327 ps
CPU time 0.98 seconds
Started Aug 23 06:15:41 AM UTC 24
Finished Aug 23 06:15:43 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664052321 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_idle_intersig_mubi.3664052321
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.1150814321
Short name T407
Test name
Test status
Simulation time 104734438 ps
CPU time 0.91 seconds
Started Aug 23 06:15:41 AM UTC 24
Finished Aug 23 06:15:43 AM UTC 24
Peak memory 209968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150814321
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_lc_clk_byp_req_intersig_mubi.1150814321
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.2780511462
Short name T406
Test name
Test status
Simulation time 25292202 ps
CPU time 0.79 seconds
Started Aug 23 06:15:41 AM UTC 24
Finished Aug 23 06:15:43 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780511462
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_lc_ctrl_intersig_mubi.2780511462
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/22.clkmgr_peri.1085449035
Short name T400
Test name
Test status
Simulation time 54484737 ps
CPU time 0.75 seconds
Started Aug 23 06:15:38 AM UTC 24
Finished Aug 23 06:15:40 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085449035 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.1085449035
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/22.clkmgr_regwen.2050617822
Short name T409
Test name
Test status
Simulation time 157181792 ps
CPU time 1.22 seconds
Started Aug 23 06:15:41 AM UTC 24
Finished Aug 23 06:15:43 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050617822 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.2050617822
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/22.clkmgr_smoke.1863747730
Short name T399
Test name
Test status
Simulation time 53664107 ps
CPU time 0.78 seconds
Started Aug 23 06:15:38 AM UTC 24
Finished Aug 23 06:15:40 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863747730 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.1863747730
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all.2784631024
Short name T438
Test name
Test status
Simulation time 1818883338 ps
CPU time 9.76 seconds
Started Aug 23 06:15:42 AM UTC 24
Finished Aug 23 06:15:53 AM UTC 24
Peak memory 210584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784631024 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all.2784631024
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all_with_rand_reset.3734189300
Short name T751
Test name
Test status
Simulation time 19261469920 ps
CPU time 124.92 seconds
Started Aug 23 06:15:41 AM UTC 24
Finished Aug 23 06:17:48 AM UTC 24
Peak memory 230180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734189300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.3734189300
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/22.clkmgr_trans.3909075438
Short name T402
Test name
Test status
Simulation time 57480565 ps
CPU time 0.83 seconds
Started Aug 23 06:15:38 AM UTC 24
Finished Aug 23 06:15:40 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909075438 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.3909075438
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/22.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/23.clkmgr_alert_test.521672601
Short name T422
Test name
Test status
Simulation time 15290047 ps
CPU time 0.66 seconds
Started Aug 23 06:15:48 AM UTC 24
Finished Aug 23 06:15:49 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521672601 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_alert_test.521672601
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.3054754201
Short name T420
Test name
Test status
Simulation time 14181547 ps
CPU time 0.67 seconds
Started Aug 23 06:15:46 AM UTC 24
Finished Aug 23 06:15:48 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054754201 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_handshake_intersig_mubi.3054754201
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/23.clkmgr_clk_status.3486751211
Short name T413
Test name
Test status
Simulation time 38547874 ps
CPU time 0.65 seconds
Started Aug 23 06:15:44 AM UTC 24
Finished Aug 23 06:15:45 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486751211 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.3486751211
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/23.clkmgr_div_intersig_mubi.1377082905
Short name T421
Test name
Test status
Simulation time 175161198 ps
CPU time 1.06 seconds
Started Aug 23 06:15:46 AM UTC 24
Finished Aug 23 06:15:48 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377082905 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_div_intersig_mubi.1377082905
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/23.clkmgr_extclk.3458664427
Short name T414
Test name
Test status
Simulation time 40580703 ps
CPU time 0.8 seconds
Started Aug 23 06:15:44 AM UTC 24
Finished Aug 23 06:15:45 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458664427 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.3458664427
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/23.clkmgr_frequency.2133624183
Short name T426
Test name
Test status
Simulation time 1080996097 ps
CPU time 5.13 seconds
Started Aug 23 06:15:44 AM UTC 24
Finished Aug 23 06:15:50 AM UTC 24
Peak memory 210624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133624183 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.2133624183
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/23.clkmgr_frequency_timeout.4167054109
Short name T436
Test name
Test status
Simulation time 1591356035 ps
CPU time 8.11 seconds
Started Aug 23 06:15:44 AM UTC 24
Finished Aug 23 06:15:53 AM UTC 24
Peak memory 210384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167054109 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_timeout.4167054109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/23.clkmgr_idle_intersig_mubi.2640917758
Short name T415
Test name
Test status
Simulation time 30626372 ps
CPU time 0.69 seconds
Started Aug 23 06:15:44 AM UTC 24
Finished Aug 23 06:15:46 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640917758 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_idle_intersig_mubi.2640917758
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.1246022996
Short name T419
Test name
Test status
Simulation time 12954684 ps
CPU time 0.64 seconds
Started Aug 23 06:15:46 AM UTC 24
Finished Aug 23 06:15:48 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246022996
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_lc_clk_byp_req_intersig_mubi.1246022996
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.567082121
Short name T417
Test name
Test status
Simulation time 63762061 ps
CPU time 0.85 seconds
Started Aug 23 06:15:45 AM UTC 24
Finished Aug 23 06:15:47 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567082121 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_lc_ctrl_intersig_mubi.567082121
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/23.clkmgr_peri.3447159489
Short name T412
Test name
Test status
Simulation time 30569953 ps
CPU time 0.66 seconds
Started Aug 23 06:15:44 AM UTC 24
Finished Aug 23 06:15:45 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447159489 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.3447159489
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/23.clkmgr_regwen.634359688
Short name T435
Test name
Test status
Simulation time 1027001126 ps
CPU time 5.35 seconds
Started Aug 23 06:15:46 AM UTC 24
Finished Aug 23 06:15:53 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634359688 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.634359688
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/23.clkmgr_smoke.1222577801
Short name T411
Test name
Test status
Simulation time 20018775 ps
CPU time 0.77 seconds
Started Aug 23 06:15:44 AM UTC 24
Finished Aug 23 06:15:45 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222577801 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.1222577801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all.1399688625
Short name T664
Test name
Test status
Simulation time 12391607872 ps
CPU time 87.95 seconds
Started Aug 23 06:15:48 AM UTC 24
Finished Aug 23 06:17:17 AM UTC 24
Peak memory 210928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399688625 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all.1399688625
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all_with_rand_reset.2243621572
Short name T517
Test name
Test status
Simulation time 4431843543 ps
CPU time 36.62 seconds
Started Aug 23 06:15:46 AM UTC 24
Finished Aug 23 06:16:24 AM UTC 24
Peak memory 226728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243621572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.2243621572
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/23.clkmgr_trans.2764499469
Short name T416
Test name
Test status
Simulation time 150760955 ps
CPU time 1.21 seconds
Started Aug 23 06:15:44 AM UTC 24
Finished Aug 23 06:15:46 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764499469 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.2764499469
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/23.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/24.clkmgr_alert_test.1861517274
Short name T440
Test name
Test status
Simulation time 22808580 ps
CPU time 0.66 seconds
Started Aug 23 06:15:54 AM UTC 24
Finished Aug 23 06:15:56 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861517274 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_alert_test.1861517274
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.2284995244
Short name T434
Test name
Test status
Simulation time 58464780 ps
CPU time 0.81 seconds
Started Aug 23 06:15:51 AM UTC 24
Finished Aug 23 06:15:53 AM UTC 24
Peak memory 209004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284995244 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_handshake_intersig_mubi.2284995244
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/24.clkmgr_clk_status.4232805938
Short name T430
Test name
Test status
Simulation time 35562748 ps
CPU time 0.64 seconds
Started Aug 23 06:15:51 AM UTC 24
Finished Aug 23 06:15:52 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232805938 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.4232805938
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/24.clkmgr_div_intersig_mubi.1671528066
Short name T433
Test name
Test status
Simulation time 23943525 ps
CPU time 0.73 seconds
Started Aug 23 06:15:51 AM UTC 24
Finished Aug 23 06:15:53 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671528066 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_div_intersig_mubi.1671528066
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/24.clkmgr_extclk.3072033029
Short name T428
Test name
Test status
Simulation time 98448305 ps
CPU time 1.03 seconds
Started Aug 23 06:15:49 AM UTC 24
Finished Aug 23 06:15:51 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072033029 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.3072033029
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/24.clkmgr_frequency.2780338233
Short name T456
Test name
Test status
Simulation time 2120160236 ps
CPU time 11.7 seconds
Started Aug 23 06:15:49 AM UTC 24
Finished Aug 23 06:16:02 AM UTC 24
Peak memory 210468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780338233 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.2780338233
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/24.clkmgr_frequency_timeout.627447094
Short name T454
Test name
Test status
Simulation time 1342733635 ps
CPU time 9.23 seconds
Started Aug 23 06:15:49 AM UTC 24
Finished Aug 23 06:15:59 AM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627447094 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_timeout.627447094
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/24.clkmgr_idle_intersig_mubi.3388695234
Short name T437
Test name
Test status
Simulation time 159636405 ps
CPU time 1.17 seconds
Started Aug 23 06:15:51 AM UTC 24
Finished Aug 23 06:15:53 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388695234 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_idle_intersig_mubi.3388695234
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.3668379579
Short name T432
Test name
Test status
Simulation time 21041768 ps
CPU time 0.75 seconds
Started Aug 23 06:15:51 AM UTC 24
Finished Aug 23 06:15:53 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668379579
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_clk_byp_req_intersig_mubi.3668379579
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.1708662499
Short name T431
Test name
Test status
Simulation time 25019015 ps
CPU time 0.75 seconds
Started Aug 23 06:15:51 AM UTC 24
Finished Aug 23 06:15:52 AM UTC 24
Peak memory 209004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708662499
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_ctrl_intersig_mubi.1708662499
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/24.clkmgr_peri.1121017804
Short name T427
Test name
Test status
Simulation time 40819863 ps
CPU time 0.76 seconds
Started Aug 23 06:15:49 AM UTC 24
Finished Aug 23 06:15:51 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121017804 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.1121017804
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/24.clkmgr_regwen.3741675785
Short name T442
Test name
Test status
Simulation time 806611240 ps
CPU time 3.43 seconds
Started Aug 23 06:15:52 AM UTC 24
Finished Aug 23 06:15:57 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741675785 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.3741675785
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/24.clkmgr_smoke.3242134833
Short name T424
Test name
Test status
Simulation time 25225056 ps
CPU time 0.81 seconds
Started Aug 23 06:15:48 AM UTC 24
Finished Aug 23 06:15:49 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242134833 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.3242134833
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all.396806833
Short name T530
Test name
Test status
Simulation time 8961582342 ps
CPU time 34.87 seconds
Started Aug 23 06:15:52 AM UTC 24
Finished Aug 23 06:16:28 AM UTC 24
Peak memory 210736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396806833 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all.396806833
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all_with_rand_reset.1838873233
Short name T609
Test name
Test status
Simulation time 4577268011 ps
CPU time 63.05 seconds
Started Aug 23 06:15:52 AM UTC 24
Finished Aug 23 06:16:57 AM UTC 24
Peak memory 220324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838873233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.1838873233
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/24.clkmgr_trans.2232450017
Short name T429
Test name
Test status
Simulation time 112435781 ps
CPU time 1.13 seconds
Started Aug 23 06:15:49 AM UTC 24
Finished Aug 23 06:15:51 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232450017 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.2232450017
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/24.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/25.clkmgr_alert_test.932143528
Short name T459
Test name
Test status
Simulation time 69137117 ps
CPU time 0.8 seconds
Started Aug 23 06:16:00 AM UTC 24
Finished Aug 23 06:16:02 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932143528 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_alert_test.932143528
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.2785066626
Short name T458
Test name
Test status
Simulation time 23462477 ps
CPU time 0.81 seconds
Started Aug 23 06:16:00 AM UTC 24
Finished Aug 23 06:16:02 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785066626 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_handshake_intersig_mubi.2785066626
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/25.clkmgr_clk_status.3975963050
Short name T446
Test name
Test status
Simulation time 48788449 ps
CPU time 0.73 seconds
Started Aug 23 06:15:56 AM UTC 24
Finished Aug 23 06:15:57 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975963050 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.3975963050
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/25.clkmgr_div_intersig_mubi.3396232070
Short name T457
Test name
Test status
Simulation time 14315381 ps
CPU time 0.64 seconds
Started Aug 23 06:16:00 AM UTC 24
Finished Aug 23 06:16:02 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396232070 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_div_intersig_mubi.3396232070
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/25.clkmgr_extclk.2513407143
Short name T444
Test name
Test status
Simulation time 27735032 ps
CPU time 0.85 seconds
Started Aug 23 06:15:55 AM UTC 24
Finished Aug 23 06:15:57 AM UTC 24
Peak memory 209968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513407143 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.2513407143
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/25.clkmgr_frequency.2441125424
Short name T450
Test name
Test status
Simulation time 380167780 ps
CPU time 1.92 seconds
Started Aug 23 06:15:55 AM UTC 24
Finished Aug 23 06:15:58 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2441125424 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.2441125424
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/25.clkmgr_frequency_timeout.2796742202
Short name T468
Test name
Test status
Simulation time 1100341736 ps
CPU time 8.45 seconds
Started Aug 23 06:15:55 AM UTC 24
Finished Aug 23 06:16:05 AM UTC 24
Peak memory 210108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796742202 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_timeout.2796742202
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/25.clkmgr_idle_intersig_mubi.202262176
Short name T448
Test name
Test status
Simulation time 35376186 ps
CPU time 0.99 seconds
Started Aug 23 06:15:56 AM UTC 24
Finished Aug 23 06:15:58 AM UTC 24
Peak memory 210516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202262176 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_idle_intersig_mubi.202262176
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.3701280497
Short name T452
Test name
Test status
Simulation time 87672555 ps
CPU time 0.99 seconds
Started Aug 23 06:15:57 AM UTC 24
Finished Aug 23 06:15:59 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701280497
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_clk_byp_req_intersig_mubi.3701280497
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.3351909226
Short name T451
Test name
Test status
Simulation time 69672712 ps
CPU time 0.89 seconds
Started Aug 23 06:15:57 AM UTC 24
Finished Aug 23 06:15:59 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351909226
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_ctrl_intersig_mubi.3351909226
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/25.clkmgr_peri.2715340948
Short name T447
Test name
Test status
Simulation time 65845402 ps
CPU time 0.79 seconds
Started Aug 23 06:15:56 AM UTC 24
Finished Aug 23 06:15:57 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715340948 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.2715340948
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/25.clkmgr_regwen.775876898
Short name T465
Test name
Test status
Simulation time 374890373 ps
CPU time 1.89 seconds
Started Aug 23 06:16:00 AM UTC 24
Finished Aug 23 06:16:03 AM UTC 24
Peak memory 209972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775876898 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.775876898
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/25.clkmgr_smoke.3260894995
Short name T443
Test name
Test status
Simulation time 23900735 ps
CPU time 0.78 seconds
Started Aug 23 06:15:55 AM UTC 24
Finished Aug 23 06:15:57 AM UTC 24
Peak memory 209928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260894995 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.3260894995
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all.2836288306
Short name T600
Test name
Test status
Simulation time 14286292613 ps
CPU time 52.82 seconds
Started Aug 23 06:16:00 AM UTC 24
Finished Aug 23 06:16:55 AM UTC 24
Peak memory 210744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836288306 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all.2836288306
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all_with_rand_reset.3110901154
Short name T556
Test name
Test status
Simulation time 3130638892 ps
CPU time 36.2 seconds
Started Aug 23 06:16:00 AM UTC 24
Finished Aug 23 06:16:38 AM UTC 24
Peak memory 220456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110901154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.3110901154
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/25.clkmgr_trans.3771220846
Short name T445
Test name
Test status
Simulation time 24363365 ps
CPU time 0.75 seconds
Started Aug 23 06:15:56 AM UTC 24
Finished Aug 23 06:15:57 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771220846 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.3771220846
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/25.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/26.clkmgr_alert_test.1824363287
Short name T472
Test name
Test status
Simulation time 14458142 ps
CPU time 0.67 seconds
Started Aug 23 06:16:06 AM UTC 24
Finished Aug 23 06:16:07 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824363287 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_alert_test.1824363287
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.651687323
Short name T471
Test name
Test status
Simulation time 26882645 ps
CPU time 0.66 seconds
Started Aug 23 06:16:05 AM UTC 24
Finished Aug 23 06:16:07 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651687323 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_handshake_intersig_mubi.651687323
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/26.clkmgr_clk_status.3659178931
Short name T461
Test name
Test status
Simulation time 42815018 ps
CPU time 0.68 seconds
Started Aug 23 06:16:01 AM UTC 24
Finished Aug 23 06:16:02 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659178931 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.3659178931
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/26.clkmgr_div_intersig_mubi.3685495816
Short name T473
Test name
Test status
Simulation time 22175478 ps
CPU time 0.71 seconds
Started Aug 23 06:16:06 AM UTC 24
Finished Aug 23 06:16:07 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685495816 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_div_intersig_mubi.3685495816
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/26.clkmgr_extclk.589751038
Short name T396
Test name
Test status
Simulation time 26961626 ps
CPU time 0.64 seconds
Started Aug 23 06:16:01 AM UTC 24
Finished Aug 23 06:16:02 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589751038 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.589751038
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/26.clkmgr_frequency.1381233010
Short name T487
Test name
Test status
Simulation time 2384491138 ps
CPU time 9.81 seconds
Started Aug 23 06:16:01 AM UTC 24
Finished Aug 23 06:16:12 AM UTC 24
Peak memory 210896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381233010 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.1381233010
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/26.clkmgr_frequency_timeout.2805757049
Short name T479
Test name
Test status
Simulation time 1664484927 ps
CPU time 6.15 seconds
Started Aug 23 06:16:01 AM UTC 24
Finished Aug 23 06:16:08 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805757049 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_timeout.2805757049
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/26.clkmgr_idle_intersig_mubi.1506937883
Short name T469
Test name
Test status
Simulation time 195131619 ps
CPU time 1.19 seconds
Started Aug 23 06:16:03 AM UTC 24
Finished Aug 23 06:16:05 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506937883 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_idle_intersig_mubi.1506937883
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.1636403762
Short name T467
Test name
Test status
Simulation time 36655296 ps
CPU time 0.77 seconds
Started Aug 23 06:16:03 AM UTC 24
Finished Aug 23 06:16:05 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636403762
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_clk_byp_req_intersig_mubi.1636403762
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.1351948775
Short name T466
Test name
Test status
Simulation time 24826747 ps
CPU time 0.77 seconds
Started Aug 23 06:16:03 AM UTC 24
Finished Aug 23 06:16:05 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351948775
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_ctrl_intersig_mubi.1351948775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/26.clkmgr_peri.3786834672
Short name T462
Test name
Test status
Simulation time 42818073 ps
CPU time 0.72 seconds
Started Aug 23 06:16:01 AM UTC 24
Finished Aug 23 06:16:02 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786834672 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.3786834672
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/26.clkmgr_regwen.3694693227
Short name T488
Test name
Test status
Simulation time 980283485 ps
CPU time 5.34 seconds
Started Aug 23 06:16:06 AM UTC 24
Finished Aug 23 06:16:12 AM UTC 24
Peak memory 210468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694693227 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.3694693227
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/26.clkmgr_smoke.499010414
Short name T460
Test name
Test status
Simulation time 23261306 ps
CPU time 0.76 seconds
Started Aug 23 06:16:00 AM UTC 24
Finished Aug 23 06:16:02 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499010414 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.499010414
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all.1299949045
Short name T624
Test name
Test status
Simulation time 13538271792 ps
CPU time 54.9 seconds
Started Aug 23 06:16:06 AM UTC 24
Finished Aug 23 06:17:02 AM UTC 24
Peak memory 210744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299949045 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all.1299949045
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all_with_rand_reset.1375712621
Short name T178
Test name
Test status
Simulation time 10723299240 ps
CPU time 102.2 seconds
Started Aug 23 06:16:06 AM UTC 24
Finished Aug 23 06:17:50 AM UTC 24
Peak memory 220432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375712621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.1375712621
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/26.clkmgr_trans.4142197201
Short name T464
Test name
Test status
Simulation time 135754040 ps
CPU time 1.19 seconds
Started Aug 23 06:16:01 AM UTC 24
Finished Aug 23 06:16:03 AM UTC 24
Peak memory 210564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142197201 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.4142197201
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/26.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/27.clkmgr_alert_test.1612583133
Short name T493
Test name
Test status
Simulation time 97236130 ps
CPU time 0.96 seconds
Started Aug 23 06:16:12 AM UTC 24
Finished Aug 23 06:16:14 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612583133 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_alert_test.1612583133
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.2346463963
Short name T482
Test name
Test status
Simulation time 39311169 ps
CPU time 0.82 seconds
Started Aug 23 06:16:08 AM UTC 24
Finished Aug 23 06:16:09 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346463963 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_handshake_intersig_mubi.2346463963
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/27.clkmgr_clk_status.1453778465
Short name T475
Test name
Test status
Simulation time 18304285 ps
CPU time 0.66 seconds
Started Aug 23 06:16:06 AM UTC 24
Finished Aug 23 06:16:08 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453778465 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.1453778465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/27.clkmgr_div_intersig_mubi.23447472
Short name T484
Test name
Test status
Simulation time 104794769 ps
CPU time 1.06 seconds
Started Aug 23 06:16:08 AM UTC 24
Finished Aug 23 06:16:10 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23447472 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_div_intersig_mubi.23447472
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/27.clkmgr_extclk.3282030351
Short name T476
Test name
Test status
Simulation time 23709405 ps
CPU time 0.79 seconds
Started Aug 23 06:16:06 AM UTC 24
Finished Aug 23 06:16:08 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282030351 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.3282030351
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/27.clkmgr_frequency.3043044629
Short name T485
Test name
Test status
Simulation time 737619027 ps
CPU time 3.36 seconds
Started Aug 23 06:16:06 AM UTC 24
Finished Aug 23 06:16:10 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043044629 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.3043044629
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/27.clkmgr_frequency_timeout.3827877964
Short name T499
Test name
Test status
Simulation time 1588077631 ps
CPU time 8.25 seconds
Started Aug 23 06:16:06 AM UTC 24
Finished Aug 23 06:16:15 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827877964 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_timeout.3827877964
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/27.clkmgr_idle_intersig_mubi.1881206093
Short name T483
Test name
Test status
Simulation time 125527502 ps
CPU time 1.07 seconds
Started Aug 23 06:16:07 AM UTC 24
Finished Aug 23 06:16:10 AM UTC 24
Peak memory 208360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881206093 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_idle_intersig_mubi.1881206093
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.1667340226
Short name T481
Test name
Test status
Simulation time 27116352 ps
CPU time 0.78 seconds
Started Aug 23 06:16:07 AM UTC 24
Finished Aug 23 06:16:09 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667340226
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_lc_clk_byp_req_intersig_mubi.1667340226
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.3472078465
Short name T480
Test name
Test status
Simulation time 36982048 ps
CPU time 0.71 seconds
Started Aug 23 06:16:07 AM UTC 24
Finished Aug 23 06:16:09 AM UTC 24
Peak memory 208084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472078465
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_lc_ctrl_intersig_mubi.3472078465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/27.clkmgr_peri.1836364452
Short name T477
Test name
Test status
Simulation time 71149215 ps
CPU time 0.9 seconds
Started Aug 23 06:16:06 AM UTC 24
Finished Aug 23 06:16:08 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836364452 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.1836364452
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/27.clkmgr_regwen.3056390382
Short name T497
Test name
Test status
Simulation time 410907264 ps
CPU time 2.59 seconds
Started Aug 23 06:16:11 AM UTC 24
Finished Aug 23 06:16:14 AM UTC 24
Peak memory 210484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056390382 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.3056390382
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/27.clkmgr_smoke.2511856485
Short name T474
Test name
Test status
Simulation time 15756267 ps
CPU time 0.77 seconds
Started Aug 23 06:16:06 AM UTC 24
Finished Aug 23 06:16:08 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511856485 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.2511856485
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all.871191301
Short name T529
Test name
Test status
Simulation time 4455643434 ps
CPU time 13.91 seconds
Started Aug 23 06:16:12 AM UTC 24
Finished Aug 23 06:16:27 AM UTC 24
Peak memory 210736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871191301 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all.871191301
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all_with_rand_reset.2791250923
Short name T683
Test name
Test status
Simulation time 17099252888 ps
CPU time 70.68 seconds
Started Aug 23 06:16:12 AM UTC 24
Finished Aug 23 06:17:24 AM UTC 24
Peak memory 226664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791250923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.2791250923
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/27.clkmgr_trans.403376374
Short name T478
Test name
Test status
Simulation time 68979246 ps
CPU time 0.92 seconds
Started Aug 23 06:16:06 AM UTC 24
Finished Aug 23 06:16:08 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403376374 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.403376374
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/27.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/28.clkmgr_alert_test.1933830226
Short name T505
Test name
Test status
Simulation time 34014658 ps
CPU time 0.71 seconds
Started Aug 23 06:16:18 AM UTC 24
Finished Aug 23 06:16:20 AM UTC 24
Peak memory 209856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933830226 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_alert_test.1933830226
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.3395803061
Short name T501
Test name
Test status
Simulation time 30590175 ps
CPU time 0.84 seconds
Started Aug 23 06:16:14 AM UTC 24
Finished Aug 23 06:16:16 AM UTC 24
Peak memory 209840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395803061 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_handshake_intersig_mubi.3395803061
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/28.clkmgr_clk_status.1770863175
Short name T492
Test name
Test status
Simulation time 43222950 ps
CPU time 0.7 seconds
Started Aug 23 06:16:12 AM UTC 24
Finished Aug 23 06:16:14 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770863175 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.1770863175
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/28.clkmgr_div_intersig_mubi.826115427
Short name T500
Test name
Test status
Simulation time 44814448 ps
CPU time 0.76 seconds
Started Aug 23 06:16:14 AM UTC 24
Finished Aug 23 06:16:16 AM UTC 24
Peak memory 209776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826115427 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_div_intersig_mubi.826115427
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/28.clkmgr_extclk.1700802426
Short name T489
Test name
Test status
Simulation time 27782339 ps
CPU time 0.8 seconds
Started Aug 23 06:16:12 AM UTC 24
Finished Aug 23 06:16:14 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700802426 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.1700802426
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/28.clkmgr_frequency.1907847337
Short name T503
Test name
Test status
Simulation time 1346820240 ps
CPU time 6.01 seconds
Started Aug 23 06:16:12 AM UTC 24
Finished Aug 23 06:16:19 AM UTC 24
Peak memory 210620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907847337 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.1907847337
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/28.clkmgr_frequency_timeout.2125316620
Short name T502
Test name
Test status
Simulation time 1647492700 ps
CPU time 5.72 seconds
Started Aug 23 06:16:12 AM UTC 24
Finished Aug 23 06:16:19 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125316620 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_timeout.2125316620
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/28.clkmgr_idle_intersig_mubi.891355252
Short name T495
Test name
Test status
Simulation time 55741142 ps
CPU time 0.73 seconds
Started Aug 23 06:16:12 AM UTC 24
Finished Aug 23 06:16:14 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891355252 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_idle_intersig_mubi.891355252
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.2191420084
Short name T496
Test name
Test status
Simulation time 98586330 ps
CPU time 0.96 seconds
Started Aug 23 06:16:12 AM UTC 24
Finished Aug 23 06:16:14 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191420084
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_lc_clk_byp_req_intersig_mubi.2191420084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.2721307816
Short name T498
Test name
Test status
Simulation time 174208984 ps
CPU time 1.08 seconds
Started Aug 23 06:16:12 AM UTC 24
Finished Aug 23 06:16:14 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721307816
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_lc_ctrl_intersig_mubi.2721307816
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/28.clkmgr_peri.899628092
Short name T490
Test name
Test status
Simulation time 44136618 ps
CPU time 0.74 seconds
Started Aug 23 06:16:12 AM UTC 24
Finished Aug 23 06:16:14 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899628092 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.899628092
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/28.clkmgr_regwen.1166489767
Short name T504
Test name
Test status
Simulation time 1589212141 ps
CPU time 4.79 seconds
Started Aug 23 06:16:14 AM UTC 24
Finished Aug 23 06:16:20 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166489767 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.1166489767
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/28.clkmgr_smoke.1704319881
Short name T491
Test name
Test status
Simulation time 76095874 ps
CPU time 0.85 seconds
Started Aug 23 06:16:12 AM UTC 24
Finished Aug 23 06:16:14 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704319881 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.1704319881
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all.2576461992
Short name T515
Test name
Test status
Simulation time 223063795 ps
CPU time 1.56 seconds
Started Aug 23 06:16:18 AM UTC 24
Finished Aug 23 06:16:21 AM UTC 24
Peak memory 209688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576461992 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all.2576461992
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all_with_rand_reset.3565574812
Short name T599
Test name
Test status
Simulation time 4082196539 ps
CPU time 37.51 seconds
Started Aug 23 06:16:14 AM UTC 24
Finished Aug 23 06:16:53 AM UTC 24
Peak memory 224420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565574812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.3565574812
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/28.clkmgr_trans.2832946061
Short name T494
Test name
Test status
Simulation time 59463590 ps
CPU time 0.84 seconds
Started Aug 23 06:16:12 AM UTC 24
Finished Aug 23 06:16:14 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832946061 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.2832946061
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/28.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/29.clkmgr_alert_test.1228014253
Short name T519
Test name
Test status
Simulation time 21172639 ps
CPU time 0.69 seconds
Started Aug 23 06:16:23 AM UTC 24
Finished Aug 23 06:16:25 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228014253 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_alert_test.1228014253
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.3684432287
Short name T511
Test name
Test status
Simulation time 22420766 ps
CPU time 0.72 seconds
Started Aug 23 06:16:19 AM UTC 24
Finished Aug 23 06:16:21 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684432287 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_handshake_intersig_mubi.3684432287
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/29.clkmgr_clk_status.2452255210
Short name T507
Test name
Test status
Simulation time 15394493 ps
CPU time 0.66 seconds
Started Aug 23 06:16:19 AM UTC 24
Finished Aug 23 06:16:20 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452255210 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.2452255210
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/29.clkmgr_div_intersig_mubi.842361351
Short name T518
Test name
Test status
Simulation time 23566634 ps
CPU time 0.7 seconds
Started Aug 23 06:16:23 AM UTC 24
Finished Aug 23 06:16:25 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842361351 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_div_intersig_mubi.842361351
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/29.clkmgr_extclk.2673338545
Short name T510
Test name
Test status
Simulation time 58859454 ps
CPU time 0.89 seconds
Started Aug 23 06:16:18 AM UTC 24
Finished Aug 23 06:16:21 AM UTC 24
Peak memory 210564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673338545 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.2673338545
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/29.clkmgr_frequency.336679702
Short name T538
Test name
Test status
Simulation time 2342693624 ps
CPU time 10.16 seconds
Started Aug 23 06:16:19 AM UTC 24
Finished Aug 23 06:16:30 AM UTC 24
Peak memory 211024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336679702 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.336679702
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/29.clkmgr_frequency_timeout.1423680560
Short name T516
Test name
Test status
Simulation time 307443750 ps
CPU time 1.51 seconds
Started Aug 23 06:16:19 AM UTC 24
Finished Aug 23 06:16:21 AM UTC 24
Peak memory 209736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423680560 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_timeout.1423680560
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/29.clkmgr_idle_intersig_mubi.2068417657
Short name T513
Test name
Test status
Simulation time 101136562 ps
CPU time 0.97 seconds
Started Aug 23 06:16:19 AM UTC 24
Finished Aug 23 06:16:21 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068417657 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_idle_intersig_mubi.2068417657
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.2058152745
Short name T514
Test name
Test status
Simulation time 86492795 ps
CPU time 0.96 seconds
Started Aug 23 06:16:19 AM UTC 24
Finished Aug 23 06:16:21 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058152745
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_lc_clk_byp_req_intersig_mubi.2058152745
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.643427594
Short name T512
Test name
Test status
Simulation time 28540444 ps
CPU time 0.8 seconds
Started Aug 23 06:16:19 AM UTC 24
Finished Aug 23 06:16:21 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643427594 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_lc_ctrl_intersig_mubi.643427594
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/29.clkmgr_peri.517364292
Short name T509
Test name
Test status
Simulation time 44573049 ps
CPU time 0.76 seconds
Started Aug 23 06:16:19 AM UTC 24
Finished Aug 23 06:16:21 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517364292 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.517364292
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/29.clkmgr_regwen.1190910465
Short name T528
Test name
Test status
Simulation time 329014048 ps
CPU time 2.19 seconds
Started Aug 23 06:16:23 AM UTC 24
Finished Aug 23 06:16:27 AM UTC 24
Peak memory 210292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190910465 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.1190910465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/29.clkmgr_smoke.4152044619
Short name T506
Test name
Test status
Simulation time 15930904 ps
CPU time 0.7 seconds
Started Aug 23 06:16:18 AM UTC 24
Finished Aug 23 06:16:20 AM UTC 24
Peak memory 210068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152044619 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.4152044619
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all.400853475
Short name T636
Test name
Test status
Simulation time 5955713970 ps
CPU time 44.1 seconds
Started Aug 23 06:16:23 AM UTC 24
Finished Aug 23 06:17:09 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400853475 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all.400853475
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all_with_rand_reset.1542017743
Short name T836
Test name
Test status
Simulation time 37894791977 ps
CPU time 118.61 seconds
Started Aug 23 06:16:23 AM UTC 24
Finished Aug 23 06:18:24 AM UTC 24
Peak memory 228304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542017743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.1542017743
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/29.clkmgr_trans.256456819
Short name T508
Test name
Test status
Simulation time 23902063 ps
CPU time 0.71 seconds
Started Aug 23 06:16:19 AM UTC 24
Finished Aug 23 06:16:21 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256456819 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.256456819
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/29.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_alert_test.1711880966
Short name T208
Test name
Test status
Simulation time 19058669 ps
CPU time 0.67 seconds
Started Aug 23 06:13:52 AM UTC 24
Finished Aug 23 06:13:54 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711880966 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_alert_test.1711880966
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.2506934961
Short name T206
Test name
Test status
Simulation time 20847437 ps
CPU time 0.73 seconds
Started Aug 23 06:13:50 AM UTC 24
Finished Aug 23 06:13:52 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506934961 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_handshake_intersig_mubi.2506934961
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_status.2359822887
Short name T188
Test name
Test status
Simulation time 36210280 ps
CPU time 0.66 seconds
Started Aug 23 06:13:49 AM UTC 24
Finished Aug 23 06:13:50 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359822887 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.2359822887
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_div_intersig_mubi.3322432011
Short name T207
Test name
Test status
Simulation time 78078862 ps
CPU time 0.91 seconds
Started Aug 23 06:13:50 AM UTC 24
Finished Aug 23 06:13:52 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322432011 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_div_intersig_mubi.3322432011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_extclk.3380440746
Short name T49
Test name
Test status
Simulation time 60777727 ps
CPU time 0.82 seconds
Started Aug 23 06:13:47 AM UTC 24
Finished Aug 23 06:13:48 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380440746 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.3380440746
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency.2771010084
Short name T12
Test name
Test status
Simulation time 434789036 ps
CPU time 3.76 seconds
Started Aug 23 06:13:47 AM UTC 24
Finished Aug 23 06:13:51 AM UTC 24
Peak memory 210428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771010084 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.2771010084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency_timeout.3578416405
Short name T137
Test name
Test status
Simulation time 2043684322 ps
CPU time 7.25 seconds
Started Aug 23 06:13:48 AM UTC 24
Finished Aug 23 06:13:56 AM UTC 24
Peak memory 210388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578416405 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_timeout.3578416405
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_idle_intersig_mubi.1679143105
Short name T203
Test name
Test status
Simulation time 123272365 ps
CPU time 0.95 seconds
Started Aug 23 06:13:49 AM UTC 24
Finished Aug 23 06:13:51 AM UTC 24
Peak memory 209900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679143105 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_idle_intersig_mubi.1679143105
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.1758666582
Short name T205
Test name
Test status
Simulation time 35237200 ps
CPU time 0.68 seconds
Started Aug 23 06:13:50 AM UTC 24
Finished Aug 23 06:13:52 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758666582
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_clk_byp_req_intersig_mubi.1758666582
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.2033322610
Short name T196
Test name
Test status
Simulation time 26159762 ps
CPU time 0.75 seconds
Started Aug 23 06:13:49 AM UTC 24
Finished Aug 23 06:13:51 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033322610
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_ctrl_intersig_mubi.2033322610
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_peri.3138880350
Short name T194
Test name
Test status
Simulation time 31351423 ps
CPU time 0.7 seconds
Started Aug 23 06:13:48 AM UTC 24
Finished Aug 23 06:13:49 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138880350 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.3138880350
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_regwen.916786398
Short name T94
Test name
Test status
Simulation time 786692857 ps
CPU time 4.36 seconds
Started Aug 23 06:13:51 AM UTC 24
Finished Aug 23 06:13:56 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916786398 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.916786398
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_sec_cm.1805695109
Short name T67
Test name
Test status
Simulation time 317148195 ps
CPU time 2.72 seconds
Started Aug 23 06:13:51 AM UTC 24
Finished Aug 23 06:13:55 AM UTC 24
Peak memory 242820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805695109 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_sec_cm.1805695109
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_smoke.4183237460
Short name T47
Test name
Test status
Simulation time 20755474 ps
CPU time 0.73 seconds
Started Aug 23 06:13:45 AM UTC 24
Finished Aug 23 06:13:47 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183237460 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.4183237460
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all_with_rand_reset.1108555205
Short name T66
Test name
Test status
Simulation time 5440131344 ps
CPU time 35.39 seconds
Started Aug 23 06:13:51 AM UTC 24
Finished Aug 23 06:14:28 AM UTC 24
Peak memory 220356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108555205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.1108555205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/3.clkmgr_trans.1875141460
Short name T204
Test name
Test status
Simulation time 27810197 ps
CPU time 0.84 seconds
Started Aug 23 06:13:48 AM UTC 24
Finished Aug 23 06:13:49 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875141460 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.1875141460
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/3.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/30.clkmgr_alert_test.3130940194
Short name T533
Test name
Test status
Simulation time 15781900 ps
CPU time 0.7 seconds
Started Aug 23 06:16:28 AM UTC 24
Finished Aug 23 06:16:30 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130940194 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_alert_test.3130940194
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.1597263793
Short name T532
Test name
Test status
Simulation time 34811458 ps
CPU time 0.81 seconds
Started Aug 23 06:16:28 AM UTC 24
Finished Aug 23 06:16:30 AM UTC 24
Peak memory 209552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597263793 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_handshake_intersig_mubi.1597263793
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/30.clkmgr_clk_status.966634690
Short name T523
Test name
Test status
Simulation time 36164759 ps
CPU time 0.69 seconds
Started Aug 23 06:16:24 AM UTC 24
Finished Aug 23 06:16:26 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966634690 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.966634690
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/30.clkmgr_div_intersig_mubi.4150523152
Short name T535
Test name
Test status
Simulation time 72288075 ps
CPU time 0.89 seconds
Started Aug 23 06:16:28 AM UTC 24
Finished Aug 23 06:16:30 AM UTC 24
Peak memory 208696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150523152 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_div_intersig_mubi.4150523152
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/30.clkmgr_extclk.1306781359
Short name T522
Test name
Test status
Simulation time 31585548 ps
CPU time 0.75 seconds
Started Aug 23 06:16:23 AM UTC 24
Finished Aug 23 06:16:26 AM UTC 24
Peak memory 209116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306781359 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.1306781359
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/30.clkmgr_frequency.2894431526
Short name T544
Test name
Test status
Simulation time 2235019153 ps
CPU time 9.99 seconds
Started Aug 23 06:16:24 AM UTC 24
Finished Aug 23 06:16:35 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894431526 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.2894431526
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/30.clkmgr_frequency_timeout.1894846433
Short name T531
Test name
Test status
Simulation time 498611906 ps
CPU time 3.96 seconds
Started Aug 23 06:16:24 AM UTC 24
Finished Aug 23 06:16:29 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894846433 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_timeout.1894846433
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/30.clkmgr_idle_intersig_mubi.345137635
Short name T527
Test name
Test status
Simulation time 102285369 ps
CPU time 1.07 seconds
Started Aug 23 06:16:24 AM UTC 24
Finished Aug 23 06:16:26 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345137635 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_idle_intersig_mubi.345137635
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.2166215245
Short name T524
Test name
Test status
Simulation time 16910588 ps
CPU time 0.7 seconds
Started Aug 23 06:16:24 AM UTC 24
Finished Aug 23 06:16:26 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166215245
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_lc_clk_byp_req_intersig_mubi.2166215245
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.4086222815
Short name T525
Test name
Test status
Simulation time 27327775 ps
CPU time 0.67 seconds
Started Aug 23 06:16:24 AM UTC 24
Finished Aug 23 06:16:26 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086222815
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_lc_ctrl_intersig_mubi.4086222815
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/30.clkmgr_peri.48197865
Short name T521
Test name
Test status
Simulation time 42057341 ps
CPU time 0.71 seconds
Started Aug 23 06:16:24 AM UTC 24
Finished Aug 23 06:16:25 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48197865 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
2/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.48197865
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/30.clkmgr_regwen.2970273801
Short name T169
Test name
Test status
Simulation time 428925162 ps
CPU time 1.85 seconds
Started Aug 23 06:16:28 AM UTC 24
Finished Aug 23 06:16:31 AM UTC 24
Peak memory 209484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970273801 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.2970273801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/30.clkmgr_smoke.2654492943
Short name T520
Test name
Test status
Simulation time 16692103 ps
CPU time 0.77 seconds
Started Aug 23 06:16:23 AM UTC 24
Finished Aug 23 06:16:25 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654492943 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.2654492943
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all.3812371408
Short name T567
Test name
Test status
Simulation time 3319695629 ps
CPU time 12.13 seconds
Started Aug 23 06:16:28 AM UTC 24
Finished Aug 23 06:16:41 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812371408 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all.3812371408
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all_with_rand_reset.2740739482
Short name T177
Test name
Test status
Simulation time 1122690059 ps
CPU time 12.8 seconds
Started Aug 23 06:16:28 AM UTC 24
Finished Aug 23 06:16:42 AM UTC 24
Peak memory 227164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740739482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.2740739482
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/30.clkmgr_trans.1201729291
Short name T526
Test name
Test status
Simulation time 46207338 ps
CPU time 0.87 seconds
Started Aug 23 06:16:24 AM UTC 24
Finished Aug 23 06:16:26 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201729291 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.1201729291
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/30.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/31.clkmgr_alert_test.3459583210
Short name T548
Test name
Test status
Simulation time 14171967 ps
CPU time 0.68 seconds
Started Aug 23 06:16:34 AM UTC 24
Finished Aug 23 06:16:36 AM UTC 24
Peak memory 209660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459583210 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_alert_test.3459583210
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.4151334598
Short name T545
Test name
Test status
Simulation time 25807781 ps
CPU time 0.66 seconds
Started Aug 23 06:16:34 AM UTC 24
Finished Aug 23 06:16:36 AM UTC 24
Peak memory 209752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151334598 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_handshake_intersig_mubi.4151334598
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/31.clkmgr_clk_status.2668417461
Short name T542
Test name
Test status
Simulation time 73478220 ps
CPU time 0.74 seconds
Started Aug 23 06:16:31 AM UTC 24
Finished Aug 23 06:16:32 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668417461 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.2668417461
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/31.clkmgr_div_intersig_mubi.2921063301
Short name T547
Test name
Test status
Simulation time 46659726 ps
CPU time 0.72 seconds
Started Aug 23 06:16:34 AM UTC 24
Finished Aug 23 06:16:36 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921063301 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_div_intersig_mubi.2921063301
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/31.clkmgr_extclk.630628731
Short name T536
Test name
Test status
Simulation time 25407343 ps
CPU time 0.78 seconds
Started Aug 23 06:16:28 AM UTC 24
Finished Aug 23 06:16:30 AM UTC 24
Peak memory 209000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630628731 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.630628731
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/31.clkmgr_frequency.838370839
Short name T539
Test name
Test status
Simulation time 451719503 ps
CPU time 1.99 seconds
Started Aug 23 06:16:28 AM UTC 24
Finished Aug 23 06:16:31 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838370839 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.838370839
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/31.clkmgr_frequency_timeout.1413666253
Short name T553
Test name
Test status
Simulation time 1102812913 ps
CPU time 8.24 seconds
Started Aug 23 06:16:28 AM UTC 24
Finished Aug 23 06:16:37 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413666253 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_timeout.1413666253
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/31.clkmgr_idle_intersig_mubi.3618079391
Short name T540
Test name
Test status
Simulation time 27828819 ps
CPU time 0.71 seconds
Started Aug 23 06:16:31 AM UTC 24
Finished Aug 23 06:16:32 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618079391 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_idle_intersig_mubi.3618079391
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.41958113
Short name T546
Test name
Test status
Simulation time 21253017 ps
CPU time 0.74 seconds
Started Aug 23 06:16:34 AM UTC 24
Finished Aug 23 06:16:36 AM UTC 24
Peak memory 209832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41958113 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_lc_clk_byp_req_intersig_mubi.41958113
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.2607514029
Short name T541
Test name
Test status
Simulation time 29932394 ps
CPU time 0.74 seconds
Started Aug 23 06:16:31 AM UTC 24
Finished Aug 23 06:16:32 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607514029
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_lc_ctrl_intersig_mubi.2607514029
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/31.clkmgr_peri.2857453697
Short name T534
Test name
Test status
Simulation time 35259510 ps
CPU time 0.72 seconds
Started Aug 23 06:16:28 AM UTC 24
Finished Aug 23 06:16:30 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857453697 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.2857453697
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/31.clkmgr_regwen.881948221
Short name T557
Test name
Test status
Simulation time 1046603586 ps
CPU time 4.41 seconds
Started Aug 23 06:16:34 AM UTC 24
Finished Aug 23 06:16:40 AM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881948221 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.881948221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/31.clkmgr_smoke.257493648
Short name T537
Test name
Test status
Simulation time 78485764 ps
CPU time 0.88 seconds
Started Aug 23 06:16:28 AM UTC 24
Finished Aug 23 06:16:30 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257493648 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.257493648
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all.1984089757
Short name T679
Test name
Test status
Simulation time 6554458667 ps
CPU time 48.51 seconds
Started Aug 23 06:16:34 AM UTC 24
Finished Aug 23 06:17:24 AM UTC 24
Peak memory 210488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984089757 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all.1984089757
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all_with_rand_reset.664620633
Short name T625
Test name
Test status
Simulation time 2974657334 ps
CPU time 28.18 seconds
Started Aug 23 06:16:34 AM UTC 24
Finished Aug 23 06:17:04 AM UTC 24
Peak memory 220548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664620633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.664620633
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/31.clkmgr_trans.3872011031
Short name T543
Test name
Test status
Simulation time 132092184 ps
CPU time 1.12 seconds
Started Aug 23 06:16:31 AM UTC 24
Finished Aug 23 06:16:33 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872011031 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.3872011031
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/31.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/32.clkmgr_alert_test.3482442391
Short name T563
Test name
Test status
Simulation time 21768788 ps
CPU time 0.68 seconds
Started Aug 23 06:16:38 AM UTC 24
Finished Aug 23 06:16:40 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482442391 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_alert_test.3482442391
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.2815712038
Short name T561
Test name
Test status
Simulation time 20046662 ps
CPU time 0.73 seconds
Started Aug 23 06:16:38 AM UTC 24
Finished Aug 23 06:16:40 AM UTC 24
Peak memory 209848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815712038 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_handshake_intersig_mubi.2815712038
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/32.clkmgr_clk_status.1393269143
Short name T554
Test name
Test status
Simulation time 53248221 ps
CPU time 0.73 seconds
Started Aug 23 06:16:36 AM UTC 24
Finished Aug 23 06:16:37 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393269143 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.1393269143
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/32.clkmgr_div_intersig_mubi.402216320
Short name T562
Test name
Test status
Simulation time 27616978 ps
CPU time 0.84 seconds
Started Aug 23 06:16:38 AM UTC 24
Finished Aug 23 06:16:40 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402216320 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_div_intersig_mubi.402216320
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/32.clkmgr_extclk.3428059613
Short name T552
Test name
Test status
Simulation time 90481688 ps
CPU time 0.95 seconds
Started Aug 23 06:16:34 AM UTC 24
Finished Aug 23 06:16:36 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428059613 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.3428059613
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/32.clkmgr_frequency.382578707
Short name T569
Test name
Test status
Simulation time 1413336764 ps
CPU time 6.2 seconds
Started Aug 23 06:16:34 AM UTC 24
Finished Aug 23 06:16:42 AM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382578707 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.382578707
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/32.clkmgr_frequency_timeout.1367604896
Short name T585
Test name
Test status
Simulation time 2181238782 ps
CPU time 10.97 seconds
Started Aug 23 06:16:34 AM UTC 24
Finished Aug 23 06:16:46 AM UTC 24
Peak memory 211088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367604896 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_timeout.1367604896
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/32.clkmgr_idle_intersig_mubi.3796585918
Short name T555
Test name
Test status
Simulation time 43754549 ps
CPU time 0.8 seconds
Started Aug 23 06:16:36 AM UTC 24
Finished Aug 23 06:16:37 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796585918 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_idle_intersig_mubi.3796585918
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.1781274147
Short name T560
Test name
Test status
Simulation time 52652435 ps
CPU time 0.77 seconds
Started Aug 23 06:16:38 AM UTC 24
Finished Aug 23 06:16:40 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781274147
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_clk_byp_req_intersig_mubi.1781274147
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.1679273835
Short name T559
Test name
Test status
Simulation time 18005482 ps
CPU time 0.7 seconds
Started Aug 23 06:16:38 AM UTC 24
Finished Aug 23 06:16:40 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679273835
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_ctrl_intersig_mubi.1679273835
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/32.clkmgr_peri.3425907982
Short name T549
Test name
Test status
Simulation time 17456104 ps
CPU time 0.63 seconds
Started Aug 23 06:16:34 AM UTC 24
Finished Aug 23 06:16:36 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425907982 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.3425907982
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/32.clkmgr_regwen.1266283080
Short name T568
Test name
Test status
Simulation time 493691152 ps
CPU time 1.88 seconds
Started Aug 23 06:16:38 AM UTC 24
Finished Aug 23 06:16:41 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266283080 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.1266283080
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/32.clkmgr_smoke.2999900193
Short name T551
Test name
Test status
Simulation time 58446056 ps
CPU time 0.87 seconds
Started Aug 23 06:16:34 AM UTC 24
Finished Aug 23 06:16:36 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999900193 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.2999900193
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all.199963143
Short name T565
Test name
Test status
Simulation time 80503082 ps
CPU time 0.94 seconds
Started Aug 23 06:16:38 AM UTC 24
Finished Aug 23 06:16:40 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199963143 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all.199963143
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all_with_rand_reset.1524054062
Short name T665
Test name
Test status
Simulation time 6716633111 ps
CPU time 38.05 seconds
Started Aug 23 06:16:38 AM UTC 24
Finished Aug 23 06:17:18 AM UTC 24
Peak memory 220324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524054062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.1524054062
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/32.clkmgr_trans.1004681811
Short name T550
Test name
Test status
Simulation time 46374604 ps
CPU time 0.74 seconds
Started Aug 23 06:16:34 AM UTC 24
Finished Aug 23 06:16:36 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004681811 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.1004681811
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/32.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/33.clkmgr_alert_test.1963410309
Short name T582
Test name
Test status
Simulation time 74308700 ps
CPU time 0.91 seconds
Started Aug 23 06:16:44 AM UTC 24
Finished Aug 23 06:16:46 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963410309 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_alert_test.1963410309
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.683466978
Short name T583
Test name
Test status
Simulation time 273525373 ps
CPU time 1.47 seconds
Started Aug 23 06:16:44 AM UTC 24
Finished Aug 23 06:16:46 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683466978 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_handshake_intersig_mubi.683466978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/33.clkmgr_clk_status.1717915217
Short name T575
Test name
Test status
Simulation time 51000491 ps
CPU time 0.72 seconds
Started Aug 23 06:16:43 AM UTC 24
Finished Aug 23 06:16:45 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717915217 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.1717915217
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/33.clkmgr_div_intersig_mubi.1966023617
Short name T578
Test name
Test status
Simulation time 23834658 ps
CPU time 0.77 seconds
Started Aug 23 06:16:44 AM UTC 24
Finished Aug 23 06:16:45 AM UTC 24
Peak memory 209972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966023617 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_div_intersig_mubi.1966023617
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/33.clkmgr_extclk.500901241
Short name T564
Test name
Test status
Simulation time 51529893 ps
CPU time 0.76 seconds
Started Aug 23 06:16:39 AM UTC 24
Finished Aug 23 06:16:40 AM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500901241 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.500901241
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/33.clkmgr_frequency.3889402897
Short name T580
Test name
Test status
Simulation time 688647044 ps
CPU time 4.16 seconds
Started Aug 23 06:16:40 AM UTC 24
Finished Aug 23 06:16:46 AM UTC 24
Peak memory 208524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889402897 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.3889402897
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/33.clkmgr_frequency_timeout.1884152231
Short name T572
Test name
Test status
Simulation time 632673281 ps
CPU time 2.93 seconds
Started Aug 23 06:16:40 AM UTC 24
Finished Aug 23 06:16:44 AM UTC 24
Peak memory 208612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884152231 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_timeout.1884152231
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/33.clkmgr_idle_intersig_mubi.4294499
Short name T577
Test name
Test status
Simulation time 33115103 ps
CPU time 0.89 seconds
Started Aug 23 06:16:43 AM UTC 24
Finished Aug 23 06:16:45 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294499 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_idle_intersig_mubi.4294499
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.1595303267
Short name T576
Test name
Test status
Simulation time 48122265 ps
CPU time 0.77 seconds
Started Aug 23 06:16:44 AM UTC 24
Finished Aug 23 06:16:45 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595303267
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_lc_clk_byp_req_intersig_mubi.1595303267
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.752748611
Short name T574
Test name
Test status
Simulation time 16310389 ps
CPU time 0.67 seconds
Started Aug 23 06:16:43 AM UTC 24
Finished Aug 23 06:16:45 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752748611 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_lc_ctrl_intersig_mubi.752748611
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/33.clkmgr_peri.4214747880
Short name T570
Test name
Test status
Simulation time 17731104 ps
CPU time 0.66 seconds
Started Aug 23 06:16:40 AM UTC 24
Finished Aug 23 06:16:42 AM UTC 24
Peak memory 209856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214747880 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.4214747880
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/33.clkmgr_regwen.1410429048
Short name T587
Test name
Test status
Simulation time 1640969103 ps
CPU time 5.38 seconds
Started Aug 23 06:16:44 AM UTC 24
Finished Aug 23 06:16:50 AM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410429048 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.1410429048
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/33.clkmgr_smoke.4014529890
Short name T566
Test name
Test status
Simulation time 83144171 ps
CPU time 0.95 seconds
Started Aug 23 06:16:39 AM UTC 24
Finished Aug 23 06:16:41 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014529890 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.4014529890
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all.3023330447
Short name T639
Test name
Test status
Simulation time 3551206784 ps
CPU time 24.77 seconds
Started Aug 23 06:16:44 AM UTC 24
Finished Aug 23 06:17:10 AM UTC 24
Peak memory 211032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023330447 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all.3023330447
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all_with_rand_reset.4241209593
Short name T668
Test name
Test status
Simulation time 2263279359 ps
CPU time 34.7 seconds
Started Aug 23 06:16:44 AM UTC 24
Finished Aug 23 06:17:20 AM UTC 24
Peak memory 227368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241209593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.4241209593
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/33.clkmgr_trans.3885652463
Short name T571
Test name
Test status
Simulation time 18000252 ps
CPU time 0.68 seconds
Started Aug 23 06:16:40 AM UTC 24
Finished Aug 23 06:16:42 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885652463 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.3885652463
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/33.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/34.clkmgr_alert_test.4252073581
Short name T594
Test name
Test status
Simulation time 17629916 ps
CPU time 0.68 seconds
Started Aug 23 06:16:49 AM UTC 24
Finished Aug 23 06:16:51 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252073581 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_alert_test.4252073581
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.296829781
Short name T592
Test name
Test status
Simulation time 44735575 ps
CPU time 0.74 seconds
Started Aug 23 06:16:49 AM UTC 24
Finished Aug 23 06:16:51 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296829781 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_handshake_intersig_mubi.296829781
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/34.clkmgr_clk_status.2361324497
Short name T588
Test name
Test status
Simulation time 19969344 ps
CPU time 0.75 seconds
Started Aug 23 06:16:49 AM UTC 24
Finished Aug 23 06:16:50 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361324497 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.2361324497
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/34.clkmgr_div_intersig_mubi.90828739
Short name T593
Test name
Test status
Simulation time 33799851 ps
CPU time 0.76 seconds
Started Aug 23 06:16:49 AM UTC 24
Finished Aug 23 06:16:51 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90828739 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_div_intersig_mubi.90828739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/34.clkmgr_extclk.213202647
Short name T579
Test name
Test status
Simulation time 19661638 ps
CPU time 0.7 seconds
Started Aug 23 06:16:44 AM UTC 24
Finished Aug 23 06:16:45 AM UTC 24
Peak memory 209000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213202647 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.213202647
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/34.clkmgr_frequency.3088885210
Short name T623
Test name
Test status
Simulation time 2235263204 ps
CPU time 15.43 seconds
Started Aug 23 06:16:45 AM UTC 24
Finished Aug 23 06:17:02 AM UTC 24
Peak memory 210360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088885210 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.3088885210
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/34.clkmgr_frequency_timeout.2359991557
Short name T610
Test name
Test status
Simulation time 1579040971 ps
CPU time 11.36 seconds
Started Aug 23 06:16:45 AM UTC 24
Finished Aug 23 06:16:58 AM UTC 24
Peak memory 210072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359991557 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_timeout.2359991557
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/34.clkmgr_idle_intersig_mubi.3485137851
Short name T589
Test name
Test status
Simulation time 37917336 ps
CPU time 0.72 seconds
Started Aug 23 06:16:49 AM UTC 24
Finished Aug 23 06:16:51 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485137851 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_idle_intersig_mubi.3485137851
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.394084606
Short name T591
Test name
Test status
Simulation time 34733485 ps
CPU time 0.71 seconds
Started Aug 23 06:16:49 AM UTC 24
Finished Aug 23 06:16:51 AM UTC 24
Peak memory 210220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394084606 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_clk_byp_req_intersig_mubi.394084606
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.3244522048
Short name T595
Test name
Test status
Simulation time 78892479 ps
CPU time 1.05 seconds
Started Aug 23 06:16:49 AM UTC 24
Finished Aug 23 06:16:51 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244522048
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_ctrl_intersig_mubi.3244522048
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/34.clkmgr_peri.711684660
Short name T586
Test name
Test status
Simulation time 80256510 ps
CPU time 0.8 seconds
Started Aug 23 06:16:45 AM UTC 24
Finished Aug 23 06:16:47 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711684660 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.711684660
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/34.clkmgr_regwen.3856359950
Short name T598
Test name
Test status
Simulation time 137752668 ps
CPU time 1.09 seconds
Started Aug 23 06:16:49 AM UTC 24
Finished Aug 23 06:16:51 AM UTC 24
Peak memory 210044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856359950 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.3856359950
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/34.clkmgr_smoke.693197272
Short name T581
Test name
Test status
Simulation time 20376643 ps
CPU time 0.77 seconds
Started Aug 23 06:16:44 AM UTC 24
Finished Aug 23 06:16:46 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693197272 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.693197272
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all.3497370249
Short name T662
Test name
Test status
Simulation time 6667156861 ps
CPU time 26.01 seconds
Started Aug 23 06:16:49 AM UTC 24
Finished Aug 23 06:17:16 AM UTC 24
Peak memory 210968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497370249 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all.3497370249
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all_with_rand_reset.1988458374
Short name T64
Test name
Test status
Simulation time 11620371367 ps
CPU time 65.98 seconds
Started Aug 23 06:16:49 AM UTC 24
Finished Aug 23 06:17:57 AM UTC 24
Peak memory 220328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988458374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.1988458374
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/34.clkmgr_trans.1460265619
Short name T590
Test name
Test status
Simulation time 54447420 ps
CPU time 0.82 seconds
Started Aug 23 06:16:49 AM UTC 24
Finished Aug 23 06:16:51 AM UTC 24
Peak memory 210564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460265619 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.1460265619
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/34.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/35.clkmgr_alert_test.1264408676
Short name T573
Test name
Test status
Simulation time 26396111 ps
CPU time 0.63 seconds
Started Aug 23 06:16:56 AM UTC 24
Finished Aug 23 06:16:58 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264408676 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_alert_test.1264408676
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.3880747530
Short name T605
Test name
Test status
Simulation time 71977516 ps
CPU time 0.91 seconds
Started Aug 23 06:16:54 AM UTC 24
Finished Aug 23 06:16:56 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880747530 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_handshake_intersig_mubi.3880747530
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/35.clkmgr_clk_status.334830447
Short name T607
Test name
Test status
Simulation time 165264799 ps
CPU time 0.96 seconds
Started Aug 23 06:16:54 AM UTC 24
Finished Aug 23 06:16:56 AM UTC 24
Peak memory 208868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334830447 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.334830447
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/35.clkmgr_div_intersig_mubi.2896219043
Short name T603
Test name
Test status
Simulation time 25144903 ps
CPU time 0.72 seconds
Started Aug 23 06:16:54 AM UTC 24
Finished Aug 23 06:16:56 AM UTC 24
Peak memory 210388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896219043 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_div_intersig_mubi.2896219043
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/35.clkmgr_extclk.3704273255
Short name T597
Test name
Test status
Simulation time 21082843 ps
CPU time 0.7 seconds
Started Aug 23 06:16:49 AM UTC 24
Finished Aug 23 06:16:51 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704273255 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.3704273255
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/35.clkmgr_frequency.1708316594
Short name T613
Test name
Test status
Simulation time 1156194237 ps
CPU time 8.8 seconds
Started Aug 23 06:16:50 AM UTC 24
Finished Aug 23 06:17:01 AM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708316594 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.1708316594
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/35.clkmgr_frequency_timeout.157290666
Short name T611
Test name
Test status
Simulation time 380591725 ps
CPU time 3.26 seconds
Started Aug 23 06:16:54 AM UTC 24
Finished Aug 23 06:16:59 AM UTC 24
Peak memory 210588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157290666 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_timeout.157290666
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/35.clkmgr_idle_intersig_mubi.2746119010
Short name T604
Test name
Test status
Simulation time 26032184 ps
CPU time 0.8 seconds
Started Aug 23 06:16:54 AM UTC 24
Finished Aug 23 06:16:56 AM UTC 24
Peak memory 210000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746119010 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_idle_intersig_mubi.2746119010
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.1473589989
Short name T602
Test name
Test status
Simulation time 22462215 ps
CPU time 0.67 seconds
Started Aug 23 06:16:54 AM UTC 24
Finished Aug 23 06:16:56 AM UTC 24
Peak memory 210448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473589989
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_lc_clk_byp_req_intersig_mubi.1473589989
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.3069984401
Short name T608
Test name
Test status
Simulation time 99843263 ps
CPU time 1.02 seconds
Started Aug 23 06:16:54 AM UTC 24
Finished Aug 23 06:16:56 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069984401
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_lc_ctrl_intersig_mubi.3069984401
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/35.clkmgr_peri.2032914418
Short name T601
Test name
Test status
Simulation time 18926543 ps
CPU time 0.71 seconds
Started Aug 23 06:16:54 AM UTC 24
Finished Aug 23 06:16:56 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032914418 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.2032914418
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/35.clkmgr_regwen.3160649263
Short name T612
Test name
Test status
Simulation time 791026546 ps
CPU time 3.32 seconds
Started Aug 23 06:16:54 AM UTC 24
Finished Aug 23 06:16:59 AM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160649263 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.3160649263
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/35.clkmgr_smoke.2329639994
Short name T596
Test name
Test status
Simulation time 29604075 ps
CPU time 0.77 seconds
Started Aug 23 06:16:49 AM UTC 24
Finished Aug 23 06:16:51 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329639994 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.2329639994
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all.3410515385
Short name T637
Test name
Test status
Simulation time 3389817544 ps
CPU time 13.69 seconds
Started Aug 23 06:16:54 AM UTC 24
Finished Aug 23 06:17:09 AM UTC 24
Peak memory 210068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410515385 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all.3410515385
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all_with_rand_reset.3063927756
Short name T843
Test name
Test status
Simulation time 10296816208 ps
CPU time 102.26 seconds
Started Aug 23 06:16:54 AM UTC 24
Finished Aug 23 06:18:39 AM UTC 24
Peak memory 220684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063927756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.3063927756
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/35.clkmgr_trans.1031815216
Short name T606
Test name
Test status
Simulation time 51123485 ps
CPU time 0.88 seconds
Started Aug 23 06:16:54 AM UTC 24
Finished Aug 23 06:16:56 AM UTC 24
Peak memory 209776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031815216 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.1031815216
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/35.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/36.clkmgr_alert_test.3250505388
Short name T627
Test name
Test status
Simulation time 34689017 ps
CPU time 0.7 seconds
Started Aug 23 06:17:04 AM UTC 24
Finished Aug 23 06:17:05 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250505388 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_alert_test.3250505388
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.3062546643
Short name T622
Test name
Test status
Simulation time 74272450 ps
CPU time 0.9 seconds
Started Aug 23 06:17:00 AM UTC 24
Finished Aug 23 06:17:02 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062546643 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_handshake_intersig_mubi.3062546643
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/36.clkmgr_clk_status.3515523063
Short name T616
Test name
Test status
Simulation time 25319433 ps
CPU time 0.64 seconds
Started Aug 23 06:17:00 AM UTC 24
Finished Aug 23 06:17:01 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515523063 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.3515523063
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/36.clkmgr_div_intersig_mubi.4057916632
Short name T620
Test name
Test status
Simulation time 29930382 ps
CPU time 0.79 seconds
Started Aug 23 06:17:00 AM UTC 24
Finished Aug 23 06:17:02 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057916632 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_div_intersig_mubi.4057916632
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/36.clkmgr_extclk.830409627
Short name T614
Test name
Test status
Simulation time 18144670 ps
CPU time 0.68 seconds
Started Aug 23 06:16:59 AM UTC 24
Finished Aug 23 06:17:01 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830409627 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.830409627
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/36.clkmgr_frequency.1447920267
Short name T660
Test name
Test status
Simulation time 1881948369 ps
CPU time 14.47 seconds
Started Aug 23 06:16:59 AM UTC 24
Finished Aug 23 06:17:15 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447920267 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.1447920267
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/36.clkmgr_frequency_timeout.3429410723
Short name T626
Test name
Test status
Simulation time 380372730 ps
CPU time 3.27 seconds
Started Aug 23 06:16:59 AM UTC 24
Finished Aug 23 06:17:04 AM UTC 24
Peak memory 210456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429410723 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_timeout.3429410723
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/36.clkmgr_idle_intersig_mubi.1933588608
Short name T617
Test name
Test status
Simulation time 21903721 ps
CPU time 0.77 seconds
Started Aug 23 06:17:00 AM UTC 24
Finished Aug 23 06:17:01 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933588608 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_idle_intersig_mubi.1933588608
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.2169752428
Short name T621
Test name
Test status
Simulation time 67535400 ps
CPU time 0.92 seconds
Started Aug 23 06:17:00 AM UTC 24
Finished Aug 23 06:17:02 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169752428
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_lc_clk_byp_req_intersig_mubi.2169752428
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.553737205
Short name T619
Test name
Test status
Simulation time 84790064 ps
CPU time 0.94 seconds
Started Aug 23 06:17:00 AM UTC 24
Finished Aug 23 06:17:02 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553737205 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_lc_ctrl_intersig_mubi.553737205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/36.clkmgr_peri.1035085759
Short name T615
Test name
Test status
Simulation time 42242130 ps
CPU time 0.73 seconds
Started Aug 23 06:16:59 AM UTC 24
Finished Aug 23 06:17:01 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035085759 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.1035085759
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/36.clkmgr_regwen.2774804883
Short name T647
Test name
Test status
Simulation time 1180644758 ps
CPU time 6.56 seconds
Started Aug 23 06:17:04 AM UTC 24
Finished Aug 23 06:17:11 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774804883 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.2774804883
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/36.clkmgr_smoke.3546146536
Short name T558
Test name
Test status
Simulation time 21377484 ps
CPU time 0.74 seconds
Started Aug 23 06:16:56 AM UTC 24
Finished Aug 23 06:16:58 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546146536 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.3546146536
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/36.clkmgr_stress_all.739793712
Short name T704
Test name
Test status
Simulation time 5229254275 ps
CPU time 25.06 seconds
Started Aug 23 06:17:04 AM UTC 24
Finished Aug 23 06:17:30 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739793712 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all.739793712
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/36.clkmgr_stress_all_with_rand_reset.1207878346
Short name T779
Test name
Test status
Simulation time 4178097043 ps
CPU time 54.53 seconds
Started Aug 23 06:17:04 AM UTC 24
Finished Aug 23 06:18:00 AM UTC 24
Peak memory 220452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207878346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.1207878346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/36.clkmgr_trans.789312991
Short name T618
Test name
Test status
Simulation time 26707317 ps
CPU time 0.83 seconds
Started Aug 23 06:16:59 AM UTC 24
Finished Aug 23 06:17:02 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789312991 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.789312991
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/36.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/37.clkmgr_alert_test.3096344473
Short name T640
Test name
Test status
Simulation time 42804108 ps
CPU time 0.72 seconds
Started Aug 23 06:17:08 AM UTC 24
Finished Aug 23 06:17:10 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096344473 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_alert_test.3096344473
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.2985231496
Short name T646
Test name
Test status
Simulation time 305020917 ps
CPU time 1.56 seconds
Started Aug 23 06:17:08 AM UTC 24
Finished Aug 23 06:17:11 AM UTC 24
Peak memory 209968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985231496 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_handshake_intersig_mubi.2985231496
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/37.clkmgr_clk_status.3508114978
Short name T631
Test name
Test status
Simulation time 38270235 ps
CPU time 0.69 seconds
Started Aug 23 06:17:04 AM UTC 24
Finished Aug 23 06:17:06 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508114978 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.3508114978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/37.clkmgr_div_intersig_mubi.1120475621
Short name T643
Test name
Test status
Simulation time 55424600 ps
CPU time 0.84 seconds
Started Aug 23 06:17:08 AM UTC 24
Finished Aug 23 06:17:10 AM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120475621 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_div_intersig_mubi.1120475621
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/37.clkmgr_extclk.2512870149
Short name T628
Test name
Test status
Simulation time 22810887 ps
CPU time 0.72 seconds
Started Aug 23 06:17:04 AM UTC 24
Finished Aug 23 06:17:05 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512870149 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.2512870149
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/37.clkmgr_frequency.3408353982
Short name T635
Test name
Test status
Simulation time 329290528 ps
CPU time 1.9 seconds
Started Aug 23 06:17:04 AM UTC 24
Finished Aug 23 06:17:07 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408353982 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.3408353982
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/37.clkmgr_frequency_timeout.3834597140
Short name T663
Test name
Test status
Simulation time 2062367700 ps
CPU time 11.63 seconds
Started Aug 23 06:17:04 AM UTC 24
Finished Aug 23 06:17:17 AM UTC 24
Peak memory 210704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834597140 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_timeout.3834597140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/37.clkmgr_idle_intersig_mubi.74670340
Short name T632
Test name
Test status
Simulation time 61988256 ps
CPU time 0.73 seconds
Started Aug 23 06:17:04 AM UTC 24
Finished Aug 23 06:17:06 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74670340 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_idle_intersig_mubi.74670340
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.2710061435
Short name T641
Test name
Test status
Simulation time 21179994 ps
CPU time 0.83 seconds
Started Aug 23 06:17:08 AM UTC 24
Finished Aug 23 06:17:10 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710061435
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_clk_byp_req_intersig_mubi.2710061435
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.1547934338
Short name T634
Test name
Test status
Simulation time 123123113 ps
CPU time 0.93 seconds
Started Aug 23 06:17:04 AM UTC 24
Finished Aug 23 06:17:06 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547934338
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_ctrl_intersig_mubi.1547934338
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/37.clkmgr_peri.2095845316
Short name T629
Test name
Test status
Simulation time 32745781 ps
CPU time 0.68 seconds
Started Aug 23 06:17:04 AM UTC 24
Finished Aug 23 06:17:06 AM UTC 24
Peak memory 208704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095845316 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.2095845316
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/37.clkmgr_regwen.2774408957
Short name T650
Test name
Test status
Simulation time 1012330048 ps
CPU time 3.49 seconds
Started Aug 23 06:17:08 AM UTC 24
Finished Aug 23 06:17:13 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774408957 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.2774408957
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/37.clkmgr_smoke.1338509431
Short name T630
Test name
Test status
Simulation time 66669362 ps
CPU time 0.88 seconds
Started Aug 23 06:17:04 AM UTC 24
Finished Aug 23 06:17:06 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338509431 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.1338509431
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all.2383698962
Short name T717
Test name
Test status
Simulation time 3525353391 ps
CPU time 26.26 seconds
Started Aug 23 06:17:08 AM UTC 24
Finished Aug 23 06:17:36 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383698962 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all.2383698962
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all_with_rand_reset.3323419975
Short name T778
Test name
Test status
Simulation time 3813620124 ps
CPU time 49.39 seconds
Started Aug 23 06:17:08 AM UTC 24
Finished Aug 23 06:17:59 AM UTC 24
Peak memory 227344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323419975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.3323419975
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/37.clkmgr_trans.2291582932
Short name T633
Test name
Test status
Simulation time 68065174 ps
CPU time 1.03 seconds
Started Aug 23 06:17:04 AM UTC 24
Finished Aug 23 06:17:06 AM UTC 24
Peak memory 208448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291582932 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.2291582932
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/37.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/38.clkmgr_alert_test.555531301
Short name T656
Test name
Test status
Simulation time 43981505 ps
CPU time 0.73 seconds
Started Aug 23 06:17:13 AM UTC 24
Finished Aug 23 06:17:15 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555531301 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_alert_test.555531301
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.153064943
Short name T655
Test name
Test status
Simulation time 60282788 ps
CPU time 0.83 seconds
Started Aug 23 06:17:13 AM UTC 24
Finished Aug 23 06:17:15 AM UTC 24
Peak memory 209980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153064943 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_handshake_intersig_mubi.153064943
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/38.clkmgr_clk_status.2958605995
Short name T652
Test name
Test status
Simulation time 16810514 ps
CPU time 0.63 seconds
Started Aug 23 06:17:13 AM UTC 24
Finished Aug 23 06:17:15 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958605995 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.2958605995
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/38.clkmgr_div_intersig_mubi.1690282520
Short name T658
Test name
Test status
Simulation time 86509779 ps
CPU time 0.95 seconds
Started Aug 23 06:17:13 AM UTC 24
Finished Aug 23 06:17:15 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690282520 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_div_intersig_mubi.1690282520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/38.clkmgr_extclk.49364498
Short name T645
Test name
Test status
Simulation time 79811620 ps
CPU time 1.01 seconds
Started Aug 23 06:17:08 AM UTC 24
Finished Aug 23 06:17:10 AM UTC 24
Peak memory 210568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49364498 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.49364498
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/38.clkmgr_frequency.399114343
Short name T661
Test name
Test status
Simulation time 1445616442 ps
CPU time 6.56 seconds
Started Aug 23 06:17:08 AM UTC 24
Finished Aug 23 06:17:16 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399114343 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.399114343
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/38.clkmgr_frequency_timeout.1805445953
Short name T649
Test name
Test status
Simulation time 383048920 ps
CPU time 2.26 seconds
Started Aug 23 06:17:08 AM UTC 24
Finished Aug 23 06:17:12 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805445953 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_timeout.1805445953
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/38.clkmgr_idle_intersig_mubi.2408705591
Short name T654
Test name
Test status
Simulation time 58350171 ps
CPU time 0.77 seconds
Started Aug 23 06:17:13 AM UTC 24
Finished Aug 23 06:17:15 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408705591 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_idle_intersig_mubi.2408705591
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.3697981875
Short name T653
Test name
Test status
Simulation time 61457253 ps
CPU time 0.8 seconds
Started Aug 23 06:17:13 AM UTC 24
Finished Aug 23 06:17:15 AM UTC 24
Peak memory 209896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697981875
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_lc_clk_byp_req_intersig_mubi.3697981875
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.1298593249
Short name T651
Test name
Test status
Simulation time 15099612 ps
CPU time 0.68 seconds
Started Aug 23 06:17:13 AM UTC 24
Finished Aug 23 06:17:15 AM UTC 24
Peak memory 209832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298593249
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_lc_ctrl_intersig_mubi.1298593249
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/38.clkmgr_peri.1190467970
Short name T644
Test name
Test status
Simulation time 24078590 ps
CPU time 0.69 seconds
Started Aug 23 06:17:08 AM UTC 24
Finished Aug 23 06:17:10 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190467970 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.1190467970
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/38.clkmgr_regwen.4267519839
Short name T666
Test name
Test status
Simulation time 631952817 ps
CPU time 3.91 seconds
Started Aug 23 06:17:13 AM UTC 24
Finished Aug 23 06:17:18 AM UTC 24
Peak memory 210568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267519839 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.4267519839
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/38.clkmgr_smoke.330518887
Short name T642
Test name
Test status
Simulation time 24046640 ps
CPU time 0.76 seconds
Started Aug 23 06:17:08 AM UTC 24
Finished Aug 23 06:17:10 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330518887 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.330518887
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all.2304634730
Short name T781
Test name
Test status
Simulation time 6557051539 ps
CPU time 46.79 seconds
Started Aug 23 06:17:13 AM UTC 24
Finished Aug 23 06:18:01 AM UTC 24
Peak memory 210744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304634730 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all.2304634730
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all_with_rand_reset.3759919490
Short name T832
Test name
Test status
Simulation time 7788270726 ps
CPU time 65.63 seconds
Started Aug 23 06:17:13 AM UTC 24
Finished Aug 23 06:18:20 AM UTC 24
Peak memory 220268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759919490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.3759919490
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/38.clkmgr_trans.320865361
Short name T648
Test name
Test status
Simulation time 63133829 ps
CPU time 0.92 seconds
Started Aug 23 06:17:09 AM UTC 24
Finished Aug 23 06:17:11 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320865361 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.320865361
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/38.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/39.clkmgr_alert_test.1026017909
Short name T684
Test name
Test status
Simulation time 46938423 ps
CPU time 0.75 seconds
Started Aug 23 06:17:23 AM UTC 24
Finished Aug 23 06:17:24 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026017909 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_alert_test.1026017909
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.2058755555
Short name T674
Test name
Test status
Simulation time 17115034 ps
CPU time 0.68 seconds
Started Aug 23 06:17:18 AM UTC 24
Finished Aug 23 06:17:20 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058755555 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_handshake_intersig_mubi.2058755555
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/39.clkmgr_clk_status.619889731
Short name T670
Test name
Test status
Simulation time 19431033 ps
CPU time 0.66 seconds
Started Aug 23 06:17:18 AM UTC 24
Finished Aug 23 06:17:20 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619889731 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.619889731
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/39.clkmgr_div_intersig_mubi.1095420349
Short name T675
Test name
Test status
Simulation time 12985788 ps
CPU time 0.66 seconds
Started Aug 23 06:17:18 AM UTC 24
Finished Aug 23 06:17:20 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095420349 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_div_intersig_mubi.1095420349
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/39.clkmgr_extclk.2931485695
Short name T657
Test name
Test status
Simulation time 28004911 ps
CPU time 0.7 seconds
Started Aug 23 06:17:13 AM UTC 24
Finished Aug 23 06:17:15 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931485695 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.2931485695
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/39.clkmgr_frequency.676904718
Short name T667
Test name
Test status
Simulation time 698978346 ps
CPU time 3.39 seconds
Started Aug 23 06:17:15 AM UTC 24
Finished Aug 23 06:17:19 AM UTC 24
Peak memory 210428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676904718 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.676904718
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/39.clkmgr_frequency_timeout.2647297807
Short name T678
Test name
Test status
Simulation time 1608660527 ps
CPU time 5.62 seconds
Started Aug 23 06:17:15 AM UTC 24
Finished Aug 23 06:17:21 AM UTC 24
Peak memory 210456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647297807 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_timeout.2647297807
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/39.clkmgr_idle_intersig_mubi.41320242
Short name T677
Test name
Test status
Simulation time 80677772 ps
CPU time 1.03 seconds
Started Aug 23 06:17:18 AM UTC 24
Finished Aug 23 06:17:20 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41320242 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_idle_intersig_mubi.41320242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.1921956593
Short name T671
Test name
Test status
Simulation time 12819521 ps
CPU time 0.64 seconds
Started Aug 23 06:17:18 AM UTC 24
Finished Aug 23 06:17:20 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921956593
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_lc_clk_byp_req_intersig_mubi.1921956593
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.4123115024
Short name T676
Test name
Test status
Simulation time 53401192 ps
CPU time 0.91 seconds
Started Aug 23 06:17:18 AM UTC 24
Finished Aug 23 06:17:20 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123115024
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_lc_ctrl_intersig_mubi.4123115024
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/39.clkmgr_peri.1439633975
Short name T673
Test name
Test status
Simulation time 56478738 ps
CPU time 0.82 seconds
Started Aug 23 06:17:18 AM UTC 24
Finished Aug 23 06:17:20 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439633975 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.1439633975
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/39.clkmgr_regwen.74287649
Short name T680
Test name
Test status
Simulation time 1293963769 ps
CPU time 4.74 seconds
Started Aug 23 06:17:18 AM UTC 24
Finished Aug 23 06:17:24 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74287649 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.74287649
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/39.clkmgr_smoke.2368243314
Short name T659
Test name
Test status
Simulation time 74372546 ps
CPU time 0.91 seconds
Started Aug 23 06:17:13 AM UTC 24
Finished Aug 23 06:17:15 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368243314 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.2368243314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/39.clkmgr_stress_all.215541029
Short name T727
Test name
Test status
Simulation time 3646078510 ps
CPU time 19.2 seconds
Started Aug 23 06:17:18 AM UTC 24
Finished Aug 23 06:17:39 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215541029 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all.215541029
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/39.clkmgr_stress_all_with_rand_reset.3943826129
Short name T732
Test name
Test status
Simulation time 4197939791 ps
CPU time 22.61 seconds
Started Aug 23 06:17:18 AM UTC 24
Finished Aug 23 06:17:42 AM UTC 24
Peak memory 220104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943826129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.3943826129
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/39.clkmgr_trans.1017659197
Short name T672
Test name
Test status
Simulation time 29033585 ps
CPU time 0.8 seconds
Started Aug 23 06:17:18 AM UTC 24
Finished Aug 23 06:17:20 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017659197 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.1017659197
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/39.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_alert_test.2631982951
Short name T174
Test name
Test status
Simulation time 18280070 ps
CPU time 0.71 seconds
Started Aug 23 06:13:59 AM UTC 24
Finished Aug 23 06:14:01 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631982951 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_alert_test.2631982951
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.591572049
Short name T162
Test name
Test status
Simulation time 35110918 ps
CPU time 0.69 seconds
Started Aug 23 06:13:57 AM UTC 24
Finished Aug 23 06:13:58 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591572049 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_handshake_intersig_mubi.591572049
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_status.398756978
Short name T189
Test name
Test status
Simulation time 46908438 ps
CPU time 0.7 seconds
Started Aug 23 06:13:55 AM UTC 24
Finished Aug 23 06:13:56 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398756978 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.398756978
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_div_intersig_mubi.3321522603
Short name T172
Test name
Test status
Simulation time 16282235 ps
CPU time 0.69 seconds
Started Aug 23 06:13:57 AM UTC 24
Finished Aug 23 06:13:58 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321522603 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_div_intersig_mubi.3321522603
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_extclk.4290529887
Short name T209
Test name
Test status
Simulation time 31566871 ps
CPU time 0.7 seconds
Started Aug 23 06:13:52 AM UTC 24
Finished Aug 23 06:13:54 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290529887 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.4290529887
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency.1823931442
Short name T37
Test name
Test status
Simulation time 683658885 ps
CPU time 5.34 seconds
Started Aug 23 06:13:52 AM UTC 24
Finished Aug 23 06:13:59 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823931442 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.1823931442
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency_timeout.696048435
Short name T136
Test name
Test status
Simulation time 163550442 ps
CPU time 1.1 seconds
Started Aug 23 06:13:53 AM UTC 24
Finished Aug 23 06:13:55 AM UTC 24
Peak memory 209732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696048435 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_timeout.696048435
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_idle_intersig_mubi.3478665730
Short name T170
Test name
Test status
Simulation time 88021976 ps
CPU time 0.96 seconds
Started Aug 23 06:13:56 AM UTC 24
Finished Aug 23 06:13:58 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478665730 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_idle_intersig_mubi.3478665730
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.703617425
Short name T171
Test name
Test status
Simulation time 38014403 ps
CPU time 0.71 seconds
Started Aug 23 06:13:57 AM UTC 24
Finished Aug 23 06:13:58 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703617425 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_clk_byp_req_intersig_mubi.703617425
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.3240010632
Short name T173
Test name
Test status
Simulation time 52501894 ps
CPU time 0.8 seconds
Started Aug 23 06:13:57 AM UTC 24
Finished Aug 23 06:13:59 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240010632
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_ctrl_intersig_mubi.3240010632
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_peri.2994781596
Short name T212
Test name
Test status
Simulation time 34502747 ps
CPU time 0.68 seconds
Started Aug 23 06:13:55 AM UTC 24
Finished Aug 23 06:13:56 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994781596 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.2994781596
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_regwen.3196279246
Short name T202
Test name
Test status
Simulation time 1134315622 ps
CPU time 4.64 seconds
Started Aug 23 06:13:57 AM UTC 24
Finished Aug 23 06:14:03 AM UTC 24
Peak memory 210704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196279246 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.3196279246
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_sec_cm.2057222979
Short name T68
Test name
Test status
Simulation time 197062994 ps
CPU time 2.04 seconds
Started Aug 23 06:13:57 AM UTC 24
Finished Aug 23 06:14:00 AM UTC 24
Peak memory 242736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057222979 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_sec_cm.2057222979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_smoke.3762393470
Short name T210
Test name
Test status
Simulation time 54754463 ps
CPU time 0.83 seconds
Started Aug 23 06:13:52 AM UTC 24
Finished Aug 23 06:13:54 AM UTC 24
Peak memory 209996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762393470 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.3762393470
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all.372276475
Short name T423
Test name
Test status
Simulation time 14555776074 ps
CPU time 108.1 seconds
Started Aug 23 06:13:59 AM UTC 24
Finished Aug 23 06:15:49 AM UTC 24
Peak memory 210932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372276475 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all.372276475
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all_with_rand_reset.1922700446
Short name T65
Test name
Test status
Simulation time 13433227443 ps
CPU time 82.28 seconds
Started Aug 23 06:13:58 AM UTC 24
Finished Aug 23 06:15:22 AM UTC 24
Peak memory 220324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922700446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.1922700446
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/4.clkmgr_trans.913666657
Short name T211
Test name
Test status
Simulation time 16887802 ps
CPU time 0.65 seconds
Started Aug 23 06:13:55 AM UTC 24
Finished Aug 23 06:13:56 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913666657 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.913666657
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/4.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/40.clkmgr_alert_test.760323450
Short name T694
Test name
Test status
Simulation time 14387938 ps
CPU time 0.65 seconds
Started Aug 23 06:17:27 AM UTC 24
Finished Aug 23 06:17:29 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760323450 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_alert_test.760323450
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.3089548015
Short name T689
Test name
Test status
Simulation time 20442298 ps
CPU time 0.73 seconds
Started Aug 23 06:17:23 AM UTC 24
Finished Aug 23 06:17:25 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089548015 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_handshake_intersig_mubi.3089548015
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/40.clkmgr_clk_status.1502490961
Short name T638
Test name
Test status
Simulation time 52738948 ps
CPU time 0.74 seconds
Started Aug 23 06:17:23 AM UTC 24
Finished Aug 23 06:17:25 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502490961 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.1502490961
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/40.clkmgr_div_intersig_mubi.516123971
Short name T691
Test name
Test status
Simulation time 65840078 ps
CPU time 0.86 seconds
Started Aug 23 06:17:23 AM UTC 24
Finished Aug 23 06:17:25 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516123971 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_div_intersig_mubi.516123971
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/40.clkmgr_extclk.207134763
Short name T686
Test name
Test status
Simulation time 58889317 ps
CPU time 0.82 seconds
Started Aug 23 06:17:23 AM UTC 24
Finished Aug 23 06:17:24 AM UTC 24
Peak memory 209420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207134763 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.207134763
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/40.clkmgr_frequency.1642946130
Short name T692
Test name
Test status
Simulation time 1058897058 ps
CPU time 4.82 seconds
Started Aug 23 06:17:23 AM UTC 24
Finished Aug 23 06:17:29 AM UTC 24
Peak memory 209904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642946130 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.1642946130
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/40.clkmgr_frequency_timeout.3324024855
Short name T705
Test name
Test status
Simulation time 1580780528 ps
CPU time 7.82 seconds
Started Aug 23 06:17:23 AM UTC 24
Finished Aug 23 06:17:32 AM UTC 24
Peak memory 210584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324024855 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_timeout.3324024855
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/40.clkmgr_idle_intersig_mubi.1810950589
Short name T688
Test name
Test status
Simulation time 48963539 ps
CPU time 0.76 seconds
Started Aug 23 06:17:23 AM UTC 24
Finished Aug 23 06:17:25 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810950589 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_idle_intersig_mubi.1810950589
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.2611892864
Short name T690
Test name
Test status
Simulation time 59903606 ps
CPU time 0.8 seconds
Started Aug 23 06:17:23 AM UTC 24
Finished Aug 23 06:17:25 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611892864
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_lc_clk_byp_req_intersig_mubi.2611892864
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.47433327
Short name T669
Test name
Test status
Simulation time 36746091 ps
CPU time 0.75 seconds
Started Aug 23 06:17:23 AM UTC 24
Finished Aug 23 06:17:25 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47433327 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_lc_ctrl_intersig_mubi.47433327
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/40.clkmgr_peri.1686395960
Short name T687
Test name
Test status
Simulation time 47612426 ps
CPU time 0.75 seconds
Started Aug 23 06:17:23 AM UTC 24
Finished Aug 23 06:17:24 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686395960 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.1686395960
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/40.clkmgr_regwen.1665068609
Short name T693
Test name
Test status
Simulation time 834044524 ps
CPU time 4.68 seconds
Started Aug 23 06:17:23 AM UTC 24
Finished Aug 23 06:17:29 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665068609 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.1665068609
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/40.clkmgr_smoke.2424894559
Short name T685
Test name
Test status
Simulation time 19231143 ps
CPU time 0.71 seconds
Started Aug 23 06:17:23 AM UTC 24
Finished Aug 23 06:17:24 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424894559 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.2424894559
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/40.clkmgr_stress_all.601908156
Short name T792
Test name
Test status
Simulation time 5164629409 ps
CPU time 35.26 seconds
Started Aug 23 06:17:27 AM UTC 24
Finished Aug 23 06:18:04 AM UTC 24
Peak memory 210824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601908156 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all.601908156
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/40.clkmgr_stress_all_with_rand_reset.1345292353
Short name T795
Test name
Test status
Simulation time 2438342072 ps
CPU time 35.91 seconds
Started Aug 23 06:17:27 AM UTC 24
Finished Aug 23 06:18:04 AM UTC 24
Peak memory 220264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345292353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.1345292353
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/40.clkmgr_trans.3423815848
Short name T681
Test name
Test status
Simulation time 18624251 ps
CPU time 0.74 seconds
Started Aug 23 06:17:23 AM UTC 24
Finished Aug 23 06:17:25 AM UTC 24
Peak memory 208616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423815848 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.3423815848
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/40.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/41.clkmgr_alert_test.1852681760
Short name T708
Test name
Test status
Simulation time 19084588 ps
CPU time 0.68 seconds
Started Aug 23 06:17:32 AM UTC 24
Finished Aug 23 06:17:33 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852681760 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_alert_test.1852681760
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.3431434965
Short name T701
Test name
Test status
Simulation time 38344294 ps
CPU time 0.77 seconds
Started Aug 23 06:17:27 AM UTC 24
Finished Aug 23 06:17:29 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431434965 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_handshake_intersig_mubi.3431434965
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/41.clkmgr_clk_status.3073380203
Short name T698
Test name
Test status
Simulation time 40049764 ps
CPU time 0.69 seconds
Started Aug 23 06:17:27 AM UTC 24
Finished Aug 23 06:17:29 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073380203 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.3073380203
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/41.clkmgr_div_intersig_mubi.2170514705
Short name T709
Test name
Test status
Simulation time 77543621 ps
CPU time 0.93 seconds
Started Aug 23 06:17:32 AM UTC 24
Finished Aug 23 06:17:34 AM UTC 24
Peak memory 209972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170514705 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_div_intersig_mubi.2170514705
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/41.clkmgr_extclk.3354286866
Short name T695
Test name
Test status
Simulation time 12974993 ps
CPU time 0.71 seconds
Started Aug 23 06:17:27 AM UTC 24
Finished Aug 23 06:17:29 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354286866 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.3354286866
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/41.clkmgr_frequency.3719698509
Short name T706
Test name
Test status
Simulation time 936897422 ps
CPU time 4.42 seconds
Started Aug 23 06:17:27 AM UTC 24
Finished Aug 23 06:17:33 AM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719698509 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.3719698509
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/41.clkmgr_frequency_timeout.506145364
Short name T707
Test name
Test status
Simulation time 614764965 ps
CPU time 4.71 seconds
Started Aug 23 06:17:27 AM UTC 24
Finished Aug 23 06:17:33 AM UTC 24
Peak memory 210464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506145364 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_timeout.506145364
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/41.clkmgr_idle_intersig_mubi.3837798337
Short name T699
Test name
Test status
Simulation time 18237116 ps
CPU time 0.73 seconds
Started Aug 23 06:17:27 AM UTC 24
Finished Aug 23 06:17:29 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837798337 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_idle_intersig_mubi.3837798337
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.3657911677
Short name T700
Test name
Test status
Simulation time 16656960 ps
CPU time 0.71 seconds
Started Aug 23 06:17:27 AM UTC 24
Finished Aug 23 06:17:29 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657911677
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_clk_byp_req_intersig_mubi.3657911677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.429127799
Short name T703
Test name
Test status
Simulation time 184702444 ps
CPU time 1.26 seconds
Started Aug 23 06:17:27 AM UTC 24
Finished Aug 23 06:17:30 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429127799 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_ctrl_intersig_mubi.429127799
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/41.clkmgr_peri.392303763
Short name T697
Test name
Test status
Simulation time 57628276 ps
CPU time 0.8 seconds
Started Aug 23 06:17:27 AM UTC 24
Finished Aug 23 06:17:29 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392303763 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.392303763
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/41.clkmgr_regwen.348688863
Short name T718
Test name
Test status
Simulation time 1274789433 ps
CPU time 4.79 seconds
Started Aug 23 06:17:32 AM UTC 24
Finished Aug 23 06:17:37 AM UTC 24
Peak memory 210872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348688863 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.348688863
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/41.clkmgr_smoke.2801588497
Short name T696
Test name
Test status
Simulation time 19667464 ps
CPU time 0.8 seconds
Started Aug 23 06:17:27 AM UTC 24
Finished Aug 23 06:17:29 AM UTC 24
Peak memory 209848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801588497 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.2801588497
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all.3523981627
Short name T741
Test name
Test status
Simulation time 2491806416 ps
CPU time 10.9 seconds
Started Aug 23 06:17:32 AM UTC 24
Finished Aug 23 06:17:44 AM UTC 24
Peak memory 210752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523981627 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all.3523981627
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all_with_rand_reset.3124889360
Short name T799
Test name
Test status
Simulation time 5382564588 ps
CPU time 32.39 seconds
Started Aug 23 06:17:32 AM UTC 24
Finished Aug 23 06:18:05 AM UTC 24
Peak memory 227196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124889360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.3124889360
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/41.clkmgr_trans.3139450727
Short name T702
Test name
Test status
Simulation time 124186565 ps
CPU time 1.1 seconds
Started Aug 23 06:17:27 AM UTC 24
Finished Aug 23 06:17:30 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139450727 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.3139450727
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/41.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/42.clkmgr_alert_test.3037063744
Short name T720
Test name
Test status
Simulation time 24700903 ps
CPU time 0.7 seconds
Started Aug 23 06:17:36 AM UTC 24
Finished Aug 23 06:17:38 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037063744 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_alert_test.3037063744
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.2035892336
Short name T723
Test name
Test status
Simulation time 77183245 ps
CPU time 0.95 seconds
Started Aug 23 06:17:36 AM UTC 24
Finished Aug 23 06:17:38 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035892336 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_handshake_intersig_mubi.2035892336
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/42.clkmgr_clk_status.450512927
Short name T712
Test name
Test status
Simulation time 19528914 ps
CPU time 0.63 seconds
Started Aug 23 06:17:32 AM UTC 24
Finished Aug 23 06:17:34 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450512927 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.450512927
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/42.clkmgr_div_intersig_mubi.2841600095
Short name T721
Test name
Test status
Simulation time 74224541 ps
CPU time 0.88 seconds
Started Aug 23 06:17:36 AM UTC 24
Finished Aug 23 06:17:38 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841600095 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_div_intersig_mubi.2841600095
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/42.clkmgr_extclk.2253996934
Short name T710
Test name
Test status
Simulation time 19154950 ps
CPU time 0.7 seconds
Started Aug 23 06:17:32 AM UTC 24
Finished Aug 23 06:17:34 AM UTC 24
Peak memory 210564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253996934 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.2253996934
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/42.clkmgr_frequency.1016806433
Short name T764
Test name
Test status
Simulation time 2355109125 ps
CPU time 18.16 seconds
Started Aug 23 06:17:32 AM UTC 24
Finished Aug 23 06:17:51 AM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016806433 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.1016806433
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/42.clkmgr_frequency_timeout.2690322112
Short name T730
Test name
Test status
Simulation time 1848383170 ps
CPU time 7.08 seconds
Started Aug 23 06:17:32 AM UTC 24
Finished Aug 23 06:17:40 AM UTC 24
Peak memory 210232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690322112 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_timeout.2690322112
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/42.clkmgr_idle_intersig_mubi.2642883574
Short name T716
Test name
Test status
Simulation time 18846409 ps
CPU time 0.72 seconds
Started Aug 23 06:17:32 AM UTC 24
Finished Aug 23 06:17:34 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642883574 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_idle_intersig_mubi.2642883574
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.1815217313
Short name T719
Test name
Test status
Simulation time 73760548 ps
CPU time 0.79 seconds
Started Aug 23 06:17:36 AM UTC 24
Finished Aug 23 06:17:38 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815217313
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_lc_clk_byp_req_intersig_mubi.1815217313
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.4137158214
Short name T714
Test name
Test status
Simulation time 27868322 ps
CPU time 0.69 seconds
Started Aug 23 06:17:32 AM UTC 24
Finished Aug 23 06:17:34 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137158214
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_lc_ctrl_intersig_mubi.4137158214
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/42.clkmgr_peri.382456957
Short name T713
Test name
Test status
Simulation time 50327232 ps
CPU time 0.76 seconds
Started Aug 23 06:17:32 AM UTC 24
Finished Aug 23 06:17:34 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382456957 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.382456957
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/42.clkmgr_regwen.4085095483
Short name T8
Test name
Test status
Simulation time 1189683572 ps
CPU time 6.05 seconds
Started Aug 23 06:17:36 AM UTC 24
Finished Aug 23 06:17:43 AM UTC 24
Peak memory 210668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085095483 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.4085095483
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/42.clkmgr_smoke.3107933209
Short name T711
Test name
Test status
Simulation time 24798237 ps
CPU time 0.81 seconds
Started Aug 23 06:17:32 AM UTC 24
Finished Aug 23 06:17:34 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107933209 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.3107933209
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all.3142709520
Short name T765
Test name
Test status
Simulation time 4568581925 ps
CPU time 17.41 seconds
Started Aug 23 06:17:36 AM UTC 24
Finished Aug 23 06:17:55 AM UTC 24
Peak memory 210628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142709520 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all.3142709520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all_with_rand_reset.204762472
Short name T846
Test name
Test status
Simulation time 13367068604 ps
CPU time 76.73 seconds
Started Aug 23 06:17:36 AM UTC 24
Finished Aug 23 06:18:55 AM UTC 24
Peak memory 221148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204762472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.204762472
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/42.clkmgr_trans.1022633912
Short name T715
Test name
Test status
Simulation time 23590262 ps
CPU time 0.75 seconds
Started Aug 23 06:17:32 AM UTC 24
Finished Aug 23 06:17:34 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022633912 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.1022633912
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/42.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/43.clkmgr_alert_test.3749171832
Short name T737
Test name
Test status
Simulation time 53850217 ps
CPU time 0.77 seconds
Started Aug 23 06:17:41 AM UTC 24
Finished Aug 23 06:17:43 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749171832 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_alert_test.3749171832
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.3805721782
Short name T734
Test name
Test status
Simulation time 35336223 ps
CPU time 0.7 seconds
Started Aug 23 06:17:41 AM UTC 24
Finished Aug 23 06:17:43 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805721782 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_handshake_intersig_mubi.3805721782
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/43.clkmgr_clk_status.4122681526
Short name T728
Test name
Test status
Simulation time 27711112 ps
CPU time 0.67 seconds
Started Aug 23 06:17:38 AM UTC 24
Finished Aug 23 06:17:39 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122681526 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.4122681526
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/43.clkmgr_div_intersig_mubi.3041297769
Short name T739
Test name
Test status
Simulation time 140888700 ps
CPU time 1.04 seconds
Started Aug 23 06:17:41 AM UTC 24
Finished Aug 23 06:17:43 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041297769 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_div_intersig_mubi.3041297769
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/43.clkmgr_extclk.2241215504
Short name T722
Test name
Test status
Simulation time 24259045 ps
CPU time 0.67 seconds
Started Aug 23 06:17:36 AM UTC 24
Finished Aug 23 06:17:38 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241215504 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.2241215504
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/43.clkmgr_frequency.1907569081
Short name T731
Test name
Test status
Simulation time 859068460 ps
CPU time 4.14 seconds
Started Aug 23 06:17:36 AM UTC 24
Finished Aug 23 06:17:41 AM UTC 24
Peak memory 210620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907569081 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.1907569081
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/43.clkmgr_frequency_timeout.3074935242
Short name T729
Test name
Test status
Simulation time 511908270 ps
CPU time 2.49 seconds
Started Aug 23 06:17:36 AM UTC 24
Finished Aug 23 06:17:40 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074935242 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_timeout.3074935242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/43.clkmgr_idle_intersig_mubi.1231403849
Short name T742
Test name
Test status
Simulation time 373039417 ps
CPU time 1.7 seconds
Started Aug 23 06:17:41 AM UTC 24
Finished Aug 23 06:17:44 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231403849 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_idle_intersig_mubi.1231403849
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.2594441998
Short name T735
Test name
Test status
Simulation time 108830670 ps
CPU time 1 seconds
Started Aug 23 06:17:41 AM UTC 24
Finished Aug 23 06:17:43 AM UTC 24
Peak memory 208916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594441998
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_clk_byp_req_intersig_mubi.2594441998
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.3209116122
Short name T733
Test name
Test status
Simulation time 20418114 ps
CPU time 0.71 seconds
Started Aug 23 06:17:41 AM UTC 24
Finished Aug 23 06:17:43 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209116122
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_ctrl_intersig_mubi.3209116122
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/43.clkmgr_peri.2014883723
Short name T724
Test name
Test status
Simulation time 33859904 ps
CPU time 0.68 seconds
Started Aug 23 06:17:36 AM UTC 24
Finished Aug 23 06:17:38 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014883723 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.2014883723
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/43.clkmgr_regwen.138553009
Short name T743
Test name
Test status
Simulation time 794578927 ps
CPU time 3.34 seconds
Started Aug 23 06:17:41 AM UTC 24
Finished Aug 23 06:17:46 AM UTC 24
Peak memory 210520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138553009 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.138553009
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/43.clkmgr_smoke.2508276783
Short name T725
Test name
Test status
Simulation time 57049186 ps
CPU time 0.85 seconds
Started Aug 23 06:17:36 AM UTC 24
Finished Aug 23 06:17:38 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508276783 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.2508276783
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all.3758748187
Short name T740
Test name
Test status
Simulation time 214028284 ps
CPU time 1.2 seconds
Started Aug 23 06:17:41 AM UTC 24
Finished Aug 23 06:17:44 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758748187 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all.3758748187
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all_with_rand_reset.1417062097
Short name T845
Test name
Test status
Simulation time 11407327128 ps
CPU time 63.81 seconds
Started Aug 23 06:17:41 AM UTC 24
Finished Aug 23 06:18:47 AM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417062097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.1417062097
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/43.clkmgr_trans.1238764036
Short name T726
Test name
Test status
Simulation time 79677439 ps
CPU time 0.87 seconds
Started Aug 23 06:17:36 AM UTC 24
Finished Aug 23 06:17:38 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238764036 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.1238764036
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/43.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/44.clkmgr_alert_test.139005548
Short name T759
Test name
Test status
Simulation time 56845424 ps
CPU time 0.83 seconds
Started Aug 23 06:17:49 AM UTC 24
Finished Aug 23 06:17:51 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139005548 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_alert_test.139005548
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.3968817657
Short name T747
Test name
Test status
Simulation time 19527767 ps
CPU time 0.71 seconds
Started Aug 23 06:17:45 AM UTC 24
Finished Aug 23 06:17:46 AM UTC 24
Peak memory 209004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968817657 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_handshake_intersig_mubi.3968817657
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/44.clkmgr_clk_status.2445158477
Short name T744
Test name
Test status
Simulation time 23057244 ps
CPU time 0.63 seconds
Started Aug 23 06:17:44 AM UTC 24
Finished Aug 23 06:17:46 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445158477 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.2445158477
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/44.clkmgr_div_intersig_mubi.2474110625
Short name T754
Test name
Test status
Simulation time 40400111 ps
CPU time 0.76 seconds
Started Aug 23 06:17:49 AM UTC 24
Finished Aug 23 06:17:51 AM UTC 24
Peak memory 210388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474110625 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_div_intersig_mubi.2474110625
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/44.clkmgr_extclk.1496626469
Short name T736
Test name
Test status
Simulation time 19449386 ps
CPU time 0.69 seconds
Started Aug 23 06:17:41 AM UTC 24
Finished Aug 23 06:17:43 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496626469 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.1496626469
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/44.clkmgr_frequency.3219810723
Short name T752
Test name
Test status
Simulation time 436358722 ps
CPU time 3.79 seconds
Started Aug 23 06:17:44 AM UTC 24
Finished Aug 23 06:17:49 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219810723 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.3219810723
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/44.clkmgr_frequency_timeout.1664381487
Short name T757
Test name
Test status
Simulation time 1382765239 ps
CPU time 6 seconds
Started Aug 23 06:17:44 AM UTC 24
Finished Aug 23 06:17:51 AM UTC 24
Peak memory 210388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664381487 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_timeout.1664381487
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/44.clkmgr_idle_intersig_mubi.1198767605
Short name T750
Test name
Test status
Simulation time 108763739 ps
CPU time 1.04 seconds
Started Aug 23 06:17:44 AM UTC 24
Finished Aug 23 06:17:47 AM UTC 24
Peak memory 208328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198767605 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_idle_intersig_mubi.1198767605
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.2226882233
Short name T748
Test name
Test status
Simulation time 40567928 ps
CPU time 0.8 seconds
Started Aug 23 06:17:45 AM UTC 24
Finished Aug 23 06:17:46 AM UTC 24
Peak memory 208464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226882233
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_clk_byp_req_intersig_mubi.2226882233
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.1335884484
Short name T749
Test name
Test status
Simulation time 26729163 ps
CPU time 0.8 seconds
Started Aug 23 06:17:44 AM UTC 24
Finished Aug 23 06:17:46 AM UTC 24
Peak memory 209532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335884484
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_ctrl_intersig_mubi.1335884484
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/44.clkmgr_peri.1387540360
Short name T745
Test name
Test status
Simulation time 18274466 ps
CPU time 0.68 seconds
Started Aug 23 06:17:44 AM UTC 24
Finished Aug 23 06:17:46 AM UTC 24
Peak memory 210116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387540360 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.1387540360
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/44.clkmgr_regwen.1672600499
Short name T773
Test name
Test status
Simulation time 1382989975 ps
CPU time 6.95 seconds
Started Aug 23 06:17:49 AM UTC 24
Finished Aug 23 06:17:57 AM UTC 24
Peak memory 210584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672600499 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.1672600499
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/44.clkmgr_smoke.1064296254
Short name T738
Test name
Test status
Simulation time 25048656 ps
CPU time 0.79 seconds
Started Aug 23 06:17:41 AM UTC 24
Finished Aug 23 06:17:43 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064296254 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.1064296254
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all.1282754747
Short name T63
Test name
Test status
Simulation time 14260195860 ps
CPU time 44.86 seconds
Started Aug 23 06:17:49 AM UTC 24
Finished Aug 23 06:18:35 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282754747 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all.1282754747
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all_with_rand_reset.1273712238
Short name T848
Test name
Test status
Simulation time 12990764945 ps
CPU time 79.69 seconds
Started Aug 23 06:17:49 AM UTC 24
Finished Aug 23 06:19:10 AM UTC 24
Peak memory 227420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273712238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.1273712238
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/44.clkmgr_trans.3907213574
Short name T746
Test name
Test status
Simulation time 22372550 ps
CPU time 0.74 seconds
Started Aug 23 06:17:44 AM UTC 24
Finished Aug 23 06:17:46 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907213574 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.3907213574
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/44.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/45.clkmgr_alert_test.3951426790
Short name T767
Test name
Test status
Simulation time 26534394 ps
CPU time 0.7 seconds
Started Aug 23 06:17:54 AM UTC 24
Finished Aug 23 06:17:55 AM UTC 24
Peak memory 209712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951426790 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_alert_test.3951426790
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.3517014141
Short name T766
Test name
Test status
Simulation time 25158747 ps
CPU time 0.77 seconds
Started Aug 23 06:17:54 AM UTC 24
Finished Aug 23 06:17:55 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517014141 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_handshake_intersig_mubi.3517014141
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/45.clkmgr_clk_status.1167257536
Short name T761
Test name
Test status
Simulation time 16826718 ps
CPU time 0.66 seconds
Started Aug 23 06:17:49 AM UTC 24
Finished Aug 23 06:17:51 AM UTC 24
Peak memory 209012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167257536 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.1167257536
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/45.clkmgr_div_intersig_mubi.2777725823
Short name T682
Test name
Test status
Simulation time 20147825 ps
CPU time 0.71 seconds
Started Aug 23 06:17:54 AM UTC 24
Finished Aug 23 06:17:55 AM UTC 24
Peak memory 210388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777725823 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_div_intersig_mubi.2777725823
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/45.clkmgr_extclk.1772095782
Short name T760
Test name
Test status
Simulation time 26231979 ps
CPU time 0.79 seconds
Started Aug 23 06:17:49 AM UTC 24
Finished Aug 23 06:17:51 AM UTC 24
Peak memory 209116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772095782 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.1772095782
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/45.clkmgr_frequency.2113713348
Short name T804
Test name
Test status
Simulation time 2476243046 ps
CPU time 18.52 seconds
Started Aug 23 06:17:49 AM UTC 24
Finished Aug 23 06:18:09 AM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113713348 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.2113713348
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/45.clkmgr_frequency_timeout.3120475739
Short name T780
Test name
Test status
Simulation time 1453925014 ps
CPU time 10.49 seconds
Started Aug 23 06:17:49 AM UTC 24
Finished Aug 23 06:18:01 AM UTC 24
Peak memory 210584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120475739 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_timeout.3120475739
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/45.clkmgr_idle_intersig_mubi.1263641166
Short name T753
Test name
Test status
Simulation time 73241666 ps
CPU time 0.92 seconds
Started Aug 23 06:17:49 AM UTC 24
Finished Aug 23 06:17:51 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263641166 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_idle_intersig_mubi.1263641166
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.3604010268
Short name T756
Test name
Test status
Simulation time 60751010 ps
CPU time 0.78 seconds
Started Aug 23 06:17:49 AM UTC 24
Finished Aug 23 06:17:51 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604010268
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_lc_clk_byp_req_intersig_mubi.3604010268
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.3236015940
Short name T763
Test name
Test status
Simulation time 16985515 ps
CPU time 0.69 seconds
Started Aug 23 06:17:49 AM UTC 24
Finished Aug 23 06:17:51 AM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236015940
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_lc_ctrl_intersig_mubi.3236015940
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/45.clkmgr_peri.1191056604
Short name T755
Test name
Test status
Simulation time 17940631 ps
CPU time 0.68 seconds
Started Aug 23 06:17:49 AM UTC 24
Finished Aug 23 06:17:51 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191056604 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.1191056604
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/45.clkmgr_regwen.1601548205
Short name T772
Test name
Test status
Simulation time 234212471 ps
CPU time 1.43 seconds
Started Aug 23 06:17:54 AM UTC 24
Finished Aug 23 06:17:56 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601548205 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.1601548205
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/45.clkmgr_smoke.676174230
Short name T758
Test name
Test status
Simulation time 29247518 ps
CPU time 0.75 seconds
Started Aug 23 06:17:49 AM UTC 24
Finished Aug 23 06:17:51 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676174230 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.676174230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all.3472151345
Short name T803
Test name
Test status
Simulation time 2541929605 ps
CPU time 12.95 seconds
Started Aug 23 06:17:54 AM UTC 24
Finished Aug 23 06:18:08 AM UTC 24
Peak memory 210376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472151345 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all.3472151345
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all_with_rand_reset.2962659348
Short name T837
Test name
Test status
Simulation time 2189463043 ps
CPU time 30.8 seconds
Started Aug 23 06:17:54 AM UTC 24
Finished Aug 23 06:18:26 AM UTC 24
Peak memory 220268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962659348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.2962659348
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/45.clkmgr_trans.1402681126
Short name T762
Test name
Test status
Simulation time 69814789 ps
CPU time 0.78 seconds
Started Aug 23 06:17:49 AM UTC 24
Finished Aug 23 06:17:51 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402681126 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.1402681126
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/45.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/46.clkmgr_alert_test.2331611409
Short name T785
Test name
Test status
Simulation time 46402159 ps
CPU time 0.74 seconds
Started Aug 23 06:18:01 AM UTC 24
Finished Aug 23 06:18:03 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331611409 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_alert_test.2331611409
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.1563022313
Short name T784
Test name
Test status
Simulation time 65942827 ps
CPU time 0.88 seconds
Started Aug 23 06:18:01 AM UTC 24
Finished Aug 23 06:18:03 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563022313 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_handshake_intersig_mubi.1563022313
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/46.clkmgr_clk_status.3901264367
Short name T774
Test name
Test status
Simulation time 14904256 ps
CPU time 0.61 seconds
Started Aug 23 06:17:56 AM UTC 24
Finished Aug 23 06:17:57 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901264367 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.3901264367
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/46.clkmgr_div_intersig_mubi.1453389440
Short name T783
Test name
Test status
Simulation time 53708166 ps
CPU time 0.79 seconds
Started Aug 23 06:18:01 AM UTC 24
Finished Aug 23 06:18:03 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453389440 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_div_intersig_mubi.1453389440
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/46.clkmgr_extclk.1853034555
Short name T769
Test name
Test status
Simulation time 22116968 ps
CPU time 0.76 seconds
Started Aug 23 06:17:54 AM UTC 24
Finished Aug 23 06:17:56 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853034555 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.1853034555
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency.3048238949
Short name T777
Test name
Test status
Simulation time 737652057 ps
CPU time 3.6 seconds
Started Aug 23 06:17:54 AM UTC 24
Finished Aug 23 06:17:59 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048238949 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.3048238949
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency_timeout.2267986081
Short name T797
Test name
Test status
Simulation time 1333160537 ps
CPU time 9.77 seconds
Started Aug 23 06:17:54 AM UTC 24
Finished Aug 23 06:18:05 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267986081 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_timeout.2267986081
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/46.clkmgr_idle_intersig_mubi.2953480535
Short name T775
Test name
Test status
Simulation time 25357598 ps
CPU time 0.67 seconds
Started Aug 23 06:17:56 AM UTC 24
Finished Aug 23 06:17:57 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953480535 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_idle_intersig_mubi.2953480535
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.2284523138
Short name T782
Test name
Test status
Simulation time 17514995 ps
CPU time 0.69 seconds
Started Aug 23 06:18:01 AM UTC 24
Finished Aug 23 06:18:03 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284523138
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_lc_clk_byp_req_intersig_mubi.2284523138
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.4131575008
Short name T776
Test name
Test status
Simulation time 52026256 ps
CPU time 0.8 seconds
Started Aug 23 06:17:56 AM UTC 24
Finished Aug 23 06:17:58 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131575008
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_lc_ctrl_intersig_mubi.4131575008
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/46.clkmgr_peri.3238441742
Short name T770
Test name
Test status
Simulation time 55716135 ps
CPU time 0.78 seconds
Started Aug 23 06:17:54 AM UTC 24
Finished Aug 23 06:17:56 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238441742 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.3238441742
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/46.clkmgr_regwen.1053594519
Short name T793
Test name
Test status
Simulation time 546720426 ps
CPU time 1.97 seconds
Started Aug 23 06:18:01 AM UTC 24
Finished Aug 23 06:18:04 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053594519 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.1053594519
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/46.clkmgr_smoke.3081210907
Short name T768
Test name
Test status
Simulation time 21789401 ps
CPU time 0.74 seconds
Started Aug 23 06:17:54 AM UTC 24
Finished Aug 23 06:17:56 AM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081210907 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.3081210907
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all.1086871004
Short name T794
Test name
Test status
Simulation time 176101799 ps
CPU time 2.16 seconds
Started Aug 23 06:18:01 AM UTC 24
Finished Aug 23 06:18:04 AM UTC 24
Peak memory 210020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086871004 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all.1086871004
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all_with_rand_reset.532489755
Short name T841
Test name
Test status
Simulation time 1950762068 ps
CPU time 32.57 seconds
Started Aug 23 06:18:01 AM UTC 24
Finished Aug 23 06:18:35 AM UTC 24
Peak memory 220332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532489755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.532489755
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/46.clkmgr_trans.234461233
Short name T771
Test name
Test status
Simulation time 21615881 ps
CPU time 0.74 seconds
Started Aug 23 06:17:54 AM UTC 24
Finished Aug 23 06:17:56 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234461233 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.234461233
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/46.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/47.clkmgr_alert_test.788119481
Short name T807
Test name
Test status
Simulation time 32017460 ps
CPU time 0.8 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:11 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788119481 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_alert_test.788119481
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.632854007
Short name T800
Test name
Test status
Simulation time 194910384 ps
CPU time 1.24 seconds
Started Aug 23 06:18:03 AM UTC 24
Finished Aug 23 06:18:05 AM UTC 24
Peak memory 209980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632854007 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_handshake_intersig_mubi.632854007
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/47.clkmgr_clk_status.2560917822
Short name T787
Test name
Test status
Simulation time 18452276 ps
CPU time 0.6 seconds
Started Aug 23 06:18:01 AM UTC 24
Finished Aug 23 06:18:03 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560917822 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.2560917822
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/47.clkmgr_div_intersig_mubi.4253480252
Short name T805
Test name
Test status
Simulation time 60500528 ps
CPU time 0.84 seconds
Started Aug 23 06:18:09 AM UTC 24
Finished Aug 23 06:18:11 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253480252 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_div_intersig_mubi.4253480252
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/47.clkmgr_extclk.1903950315
Short name T786
Test name
Test status
Simulation time 18975704 ps
CPU time 0.7 seconds
Started Aug 23 06:18:01 AM UTC 24
Finished Aug 23 06:18:03 AM UTC 24
Peak memory 209312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903950315 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.1903950315
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency.3417348162
Short name T801
Test name
Test status
Simulation time 558148378 ps
CPU time 4.18 seconds
Started Aug 23 06:18:01 AM UTC 24
Finished Aug 23 06:18:06 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417348162 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.3417348162
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency_timeout.1889486134
Short name T802
Test name
Test status
Simulation time 748098839 ps
CPU time 4.19 seconds
Started Aug 23 06:18:01 AM UTC 24
Finished Aug 23 06:18:06 AM UTC 24
Peak memory 210584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889486134 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_timeout.1889486134
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/47.clkmgr_idle_intersig_mubi.2566280136
Short name T791
Test name
Test status
Simulation time 81357855 ps
CPU time 0.91 seconds
Started Aug 23 06:18:01 AM UTC 24
Finished Aug 23 06:18:03 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566280136 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_idle_intersig_mubi.2566280136
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.3654314096
Short name T798
Test name
Test status
Simulation time 40964303 ps
CPU time 0.82 seconds
Started Aug 23 06:18:03 AM UTC 24
Finished Aug 23 06:18:05 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654314096
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_lc_clk_byp_req_intersig_mubi.3654314096
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.2260863004
Short name T796
Test name
Test status
Simulation time 23653659 ps
CPU time 0.75 seconds
Started Aug 23 06:18:03 AM UTC 24
Finished Aug 23 06:18:05 AM UTC 24
Peak memory 210000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260863004
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_lc_ctrl_intersig_mubi.2260863004
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/47.clkmgr_peri.238735301
Short name T788
Test name
Test status
Simulation time 15143678 ps
CPU time 0.65 seconds
Started Aug 23 06:18:01 AM UTC 24
Finished Aug 23 06:18:03 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238735301 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.238735301
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/47.clkmgr_regwen.4044405496
Short name T818
Test name
Test status
Simulation time 964116719 ps
CPU time 4.14 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:15 AM UTC 24
Peak memory 210604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044405496 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.4044405496
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/47.clkmgr_smoke.157778748
Short name T789
Test name
Test status
Simulation time 25349465 ps
CPU time 0.8 seconds
Started Aug 23 06:18:01 AM UTC 24
Finished Aug 23 06:18:03 AM UTC 24
Peak memory 209968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157778748 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.157778748
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all.3790019783
Short name T844
Test name
Test status
Simulation time 8435591054 ps
CPU time 32.56 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:43 AM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790019783 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all.3790019783
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all_with_rand_reset.332676282
Short name T847
Test name
Test status
Simulation time 3181465554 ps
CPU time 48.55 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:19:00 AM UTC 24
Peak memory 220272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332676282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.332676282
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/47.clkmgr_trans.3136997096
Short name T790
Test name
Test status
Simulation time 46669061 ps
CPU time 0.81 seconds
Started Aug 23 06:18:01 AM UTC 24
Finished Aug 23 06:18:03 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136997096 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.3136997096
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/47.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/48.clkmgr_alert_test.560531015
Short name T820
Test name
Test status
Simulation time 35673675 ps
CPU time 0.69 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:17 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560531015 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_alert_test.560531015
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.1009756679
Short name T812
Test name
Test status
Simulation time 25602503 ps
CPU time 0.69 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:12 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009756679 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_handshake_intersig_mubi.1009756679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_status.2208116545
Short name T809
Test name
Test status
Simulation time 41679136 ps
CPU time 0.66 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:12 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208116545 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.2208116545
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/48.clkmgr_div_intersig_mubi.656062616
Short name T814
Test name
Test status
Simulation time 24257767 ps
CPU time 0.79 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:12 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656062616 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_div_intersig_mubi.656062616
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/48.clkmgr_extclk.1962635378
Short name T808
Test name
Test status
Simulation time 20051175 ps
CPU time 0.72 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:11 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962635378 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.1962635378
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency.3663826646
Short name T819
Test name
Test status
Simulation time 810150568 ps
CPU time 4.79 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:16 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663826646 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.3663826646
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency_timeout.1975325852
Short name T838
Test name
Test status
Simulation time 2174655724 ps
CPU time 15.32 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:26 AM UTC 24
Peak memory 210984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975325852 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_timeout.1975325852
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/48.clkmgr_idle_intersig_mubi.3474826715
Short name T815
Test name
Test status
Simulation time 87305872 ps
CPU time 1 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:12 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474826715 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_idle_intersig_mubi.3474826715
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.3988423678
Short name T816
Test name
Test status
Simulation time 396005390 ps
CPU time 1.75 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:13 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988423678
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_lc_clk_byp_req_intersig_mubi.3988423678
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.1059202951
Short name T813
Test name
Test status
Simulation time 27704673 ps
CPU time 0.74 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:12 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059202951
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_lc_ctrl_intersig_mubi.1059202951
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/48.clkmgr_peri.3453005439
Short name T811
Test name
Test status
Simulation time 45401473 ps
CPU time 0.75 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:12 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453005439 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.3453005439
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/48.clkmgr_regwen.713700140
Short name T817
Test name
Test status
Simulation time 522248393 ps
CPU time 2.04 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:13 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713700140 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.713700140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/48.clkmgr_smoke.4117488429
Short name T806
Test name
Test status
Simulation time 18661051 ps
CPU time 0.72 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:11 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117488429 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.4117488429
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all.3285513499
Short name T842
Test name
Test status
Simulation time 4396062154 ps
CPU time 18.44 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:35 AM UTC 24
Peak memory 210972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285513499 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all.3285513499
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all_with_rand_reset.2102715487
Short name T179
Test name
Test status
Simulation time 2901572398 ps
CPU time 37.39 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:49 AM UTC 24
Peak memory 227468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102715487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.2102715487
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/48.clkmgr_trans.3928547696
Short name T810
Test name
Test status
Simulation time 16246793 ps
CPU time 0.7 seconds
Started Aug 23 06:18:10 AM UTC 24
Finished Aug 23 06:18:12 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928547696 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.3928547696
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/48.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/49.clkmgr_alert_test.3230070560
Short name T835
Test name
Test status
Simulation time 22893724 ps
CPU time 0.71 seconds
Started Aug 23 06:18:21 AM UTC 24
Finished Aug 23 06:18:23 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230070560 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_alert_test.3230070560
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.864944153
Short name T827
Test name
Test status
Simulation time 23518884 ps
CPU time 0.74 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:18 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864944153 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_handshake_intersig_mubi.864944153
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_status.67863878
Short name T822
Test name
Test status
Simulation time 43840713 ps
CPU time 0.7 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:18 AM UTC 24
Peak memory 209132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67863878 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.67863878
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/49.clkmgr_div_intersig_mubi.3757833711
Short name T829
Test name
Test status
Simulation time 75330781 ps
CPU time 0.93 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:18 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757833711 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_div_intersig_mubi.3757833711
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/49.clkmgr_extclk.4016123526
Short name T824
Test name
Test status
Simulation time 112965468 ps
CPU time 0.96 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:18 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016123526 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.4016123526
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency.3132369431
Short name T834
Test name
Test status
Simulation time 681084123 ps
CPU time 5.26 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:22 AM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132369431 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.3132369431
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency_timeout.1727501812
Short name T833
Test name
Test status
Simulation time 1238622128 ps
CPU time 5.24 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:22 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727501812 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_timeout.1727501812
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/49.clkmgr_idle_intersig_mubi.333183843
Short name T830
Test name
Test status
Simulation time 153323841 ps
CPU time 1.1 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:18 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333183843 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_idle_intersig_mubi.333183843
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.637909881
Short name T826
Test name
Test status
Simulation time 42373671 ps
CPU time 0.73 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:18 AM UTC 24
Peak memory 210220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637909881 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_lc_clk_byp_req_intersig_mubi.637909881
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.440044245
Short name T825
Test name
Test status
Simulation time 35647616 ps
CPU time 0.79 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:18 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440044245 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_lc_ctrl_intersig_mubi.440044245
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/49.clkmgr_peri.1062025994
Short name T823
Test name
Test status
Simulation time 44811952 ps
CPU time 0.78 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:18 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062025994 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.1062025994
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/49.clkmgr_regwen.2762311534
Short name T831
Test name
Test status
Simulation time 690007906 ps
CPU time 2.7 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:20 AM UTC 24
Peak memory 210760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762311534 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.2762311534
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/49.clkmgr_smoke.3094555850
Short name T821
Test name
Test status
Simulation time 66279000 ps
CPU time 0.86 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:17 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094555850 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.3094555850
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all.2661842003
Short name T839
Test name
Test status
Simulation time 1183044812 ps
CPU time 9.17 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:26 AM UTC 24
Peak memory 210584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661842003 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all.2661842003
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all_with_rand_reset.2482659362
Short name T840
Test name
Test status
Simulation time 863288233 ps
CPU time 10.78 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:28 AM UTC 24
Peak memory 220124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482659362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.2482659362
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/49.clkmgr_trans.2708588843
Short name T828
Test name
Test status
Simulation time 113188938 ps
CPU time 1.11 seconds
Started Aug 23 06:18:16 AM UTC 24
Finished Aug 23 06:18:18 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708588843 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.2708588843
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/49.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/5.clkmgr_alert_test.3707724751
Short name T221
Test name
Test status
Simulation time 90170488 ps
CPU time 0.85 seconds
Started Aug 23 06:14:06 AM UTC 24
Finished Aug 23 06:14:08 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707724751 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_alert_test.3707724751
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.1093344051
Short name T218
Test name
Test status
Simulation time 24523675 ps
CPU time 0.69 seconds
Started Aug 23 06:14:04 AM UTC 24
Finished Aug 23 06:14:05 AM UTC 24
Peak memory 210044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093344051 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_handshake_intersig_mubi.1093344051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_status.3841751394
Short name T190
Test name
Test status
Simulation time 54069979 ps
CPU time 0.67 seconds
Started Aug 23 06:14:01 AM UTC 24
Finished Aug 23 06:14:03 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841751394 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.3841751394
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/5.clkmgr_div_intersig_mubi.3559404829
Short name T220
Test name
Test status
Simulation time 22442860 ps
CPU time 0.77 seconds
Started Aug 23 06:14:04 AM UTC 24
Finished Aug 23 06:14:05 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559404829 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_div_intersig_mubi.3559404829
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/5.clkmgr_extclk.2997371033
Short name T213
Test name
Test status
Simulation time 23284563 ps
CPU time 0.8 seconds
Started Aug 23 06:13:59 AM UTC 24
Finished Aug 23 06:14:01 AM UTC 24
Peak memory 209816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997371033 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.2997371033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency.2059563296
Short name T13
Test name
Test status
Simulation time 704732315 ps
CPU time 3.38 seconds
Started Aug 23 06:13:59 AM UTC 24
Finished Aug 23 06:14:04 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059563296 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.2059563296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency_timeout.848159128
Short name T88
Test name
Test status
Simulation time 1458106870 ps
CPU time 10.43 seconds
Started Aug 23 06:14:00 AM UTC 24
Finished Aug 23 06:14:12 AM UTC 24
Peak memory 210392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848159128 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_timeout.848159128
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/5.clkmgr_idle_intersig_mubi.2411551016
Short name T216
Test name
Test status
Simulation time 142264910 ps
CPU time 1.11 seconds
Started Aug 23 06:14:01 AM UTC 24
Finished Aug 23 06:14:03 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411551016 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.2411551016
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.2962865226
Short name T219
Test name
Test status
Simulation time 19345227 ps
CPU time 0.72 seconds
Started Aug 23 06:14:03 AM UTC 24
Finished Aug 23 06:14:05 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962865226
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_lc_clk_byp_req_intersig_mubi.2962865226
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.4060300911
Short name T217
Test name
Test status
Simulation time 40482622 ps
CPU time 0.72 seconds
Started Aug 23 06:14:03 AM UTC 24
Finished Aug 23 06:14:05 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060300911
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_lc_ctrl_intersig_mubi.4060300911
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/5.clkmgr_peri.844151245
Short name T214
Test name
Test status
Simulation time 24104562 ps
CPU time 0.68 seconds
Started Aug 23 06:14:01 AM UTC 24
Finished Aug 23 06:14:03 AM UTC 24
Peak memory 210212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844151245 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.844151245
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/5.clkmgr_regwen.182575322
Short name T96
Test name
Test status
Simulation time 349690700 ps
CPU time 1.84 seconds
Started Aug 23 06:14:05 AM UTC 24
Finished Aug 23 06:14:07 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182575322 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.182575322
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/5.clkmgr_smoke.2955189673
Short name T175
Test name
Test status
Simulation time 45955984 ps
CPU time 0.76 seconds
Started Aug 23 06:13:59 AM UTC 24
Finished Aug 23 06:14:01 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955189673 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.2955189673
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/5.clkmgr_stress_all.1104384516
Short name T18
Test name
Test status
Simulation time 5423989411 ps
CPU time 38.13 seconds
Started Aug 23 06:14:06 AM UTC 24
Finished Aug 23 06:14:45 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104384516 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all.1104384516
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/5.clkmgr_stress_all_with_rand_reset.866469408
Short name T60
Test name
Test status
Simulation time 8383382490 ps
CPU time 54.88 seconds
Started Aug 23 06:14:05 AM UTC 24
Finished Aug 23 06:15:01 AM UTC 24
Peak memory 220400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866469408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.866469408
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/5.clkmgr_trans.1354744311
Short name T215
Test name
Test status
Simulation time 55551023 ps
CPU time 0.8 seconds
Started Aug 23 06:14:01 AM UTC 24
Finished Aug 23 06:14:03 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354744311 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.1354744311
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/5.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/6.clkmgr_alert_test.1168046075
Short name T223
Test name
Test status
Simulation time 37988007 ps
CPU time 0.69 seconds
Started Aug 23 06:14:13 AM UTC 24
Finished Aug 23 06:14:14 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168046075 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_alert_test.1168046075
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.1868879701
Short name T222
Test name
Test status
Simulation time 25597393 ps
CPU time 0.71 seconds
Started Aug 23 06:14:11 AM UTC 24
Finished Aug 23 06:14:13 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868879701 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_handshake_intersig_mubi.1868879701
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/6.clkmgr_clk_status.3357161964
Short name T87
Test name
Test status
Simulation time 19681269 ps
CPU time 0.63 seconds
Started Aug 23 06:14:09 AM UTC 24
Finished Aug 23 06:14:11 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357161964 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.3357161964
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/6.clkmgr_div_intersig_mubi.3205487992
Short name T92
Test name
Test status
Simulation time 24122621 ps
CPU time 0.69 seconds
Started Aug 23 06:14:11 AM UTC 24
Finished Aug 23 06:14:13 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205487992 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_div_intersig_mubi.3205487992
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/6.clkmgr_extclk.245506897
Short name T197
Test name
Test status
Simulation time 44749430 ps
CPU time 0.86 seconds
Started Aug 23 06:14:06 AM UTC 24
Finished Aug 23 06:14:08 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245506897 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.245506897
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency.3795138264
Short name T34
Test name
Test status
Simulation time 1074514664 ps
CPU time 4.69 seconds
Started Aug 23 06:14:08 AM UTC 24
Finished Aug 23 06:14:14 AM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795138264 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.3795138264
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency_timeout.344719132
Short name T97
Test name
Test status
Simulation time 2405738455 ps
CPU time 10 seconds
Started Aug 23 06:14:08 AM UTC 24
Finished Aug 23 06:14:19 AM UTC 24
Peak memory 210736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344719132 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_timeout.344719132
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/6.clkmgr_idle_intersig_mubi.341068111
Short name T91
Test name
Test status
Simulation time 59131832 ps
CPU time 0.84 seconds
Started Aug 23 06:14:10 AM UTC 24
Finished Aug 23 06:14:12 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341068111 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_idle_intersig_mubi.341068111
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.4290243405
Short name T90
Test name
Test status
Simulation time 45432463 ps
CPU time 0.75 seconds
Started Aug 23 06:14:10 AM UTC 24
Finished Aug 23 06:14:12 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290243405
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_lc_clk_byp_req_intersig_mubi.4290243405
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.2939502729
Short name T89
Test name
Test status
Simulation time 20076817 ps
CPU time 0.71 seconds
Started Aug 23 06:14:10 AM UTC 24
Finished Aug 23 06:14:12 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939502729
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_lc_ctrl_intersig_mubi.2939502729
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/6.clkmgr_peri.2988567173
Short name T85
Test name
Test status
Simulation time 18275153 ps
CPU time 0.65 seconds
Started Aug 23 06:14:08 AM UTC 24
Finished Aug 23 06:14:10 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988567173 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.2988567173
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/6.clkmgr_regwen.1794994596
Short name T107
Test name
Test status
Simulation time 1319873826 ps
CPU time 6.71 seconds
Started Aug 23 06:14:13 AM UTC 24
Finished Aug 23 06:14:20 AM UTC 24
Peak memory 210516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794994596 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.1794994596
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/6.clkmgr_smoke.885612673
Short name T155
Test name
Test status
Simulation time 23438534 ps
CPU time 0.75 seconds
Started Aug 23 06:14:06 AM UTC 24
Finished Aug 23 06:14:08 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885612673 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.885612673
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all.728148559
Short name T36
Test name
Test status
Simulation time 2816437397 ps
CPU time 19.53 seconds
Started Aug 23 06:14:13 AM UTC 24
Finished Aug 23 06:14:33 AM UTC 24
Peak memory 210352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728148559 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all.728148559
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all_with_rand_reset.1826201242
Short name T40
Test name
Test status
Simulation time 5267477584 ps
CPU time 32.92 seconds
Started Aug 23 06:14:13 AM UTC 24
Finished Aug 23 06:14:47 AM UTC 24
Peak memory 224052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826201242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.1826201242
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/6.clkmgr_trans.3569229346
Short name T86
Test name
Test status
Simulation time 34635212 ps
CPU time 0.88 seconds
Started Aug 23 06:14:08 AM UTC 24
Finished Aug 23 06:14:10 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569229346 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.3569229346
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/6.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/7.clkmgr_alert_test.173347646
Short name T109
Test name
Test status
Simulation time 15868599 ps
CPU time 0.65 seconds
Started Aug 23 06:14:20 AM UTC 24
Finished Aug 23 06:14:22 AM UTC 24
Peak memory 210028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173347646 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_alert_test.173347646
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.3277199620
Short name T106
Test name
Test status
Simulation time 82172744 ps
CPU time 0.91 seconds
Started Aug 23 06:14:18 AM UTC 24
Finished Aug 23 06:14:20 AM UTC 24
Peak memory 210044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277199620 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_handshake_intersig_mubi.3277199620
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_status.3589222187
Short name T191
Test name
Test status
Simulation time 23141556 ps
CPU time 0.64 seconds
Started Aug 23 06:14:16 AM UTC 24
Finished Aug 23 06:14:18 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589222187 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.3589222187
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/7.clkmgr_div_intersig_mubi.3955504873
Short name T111
Test name
Test status
Simulation time 241866640 ps
CPU time 1.3 seconds
Started Aug 23 06:14:20 AM UTC 24
Finished Aug 23 06:14:23 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955504873 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_div_intersig_mubi.3955504873
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/7.clkmgr_extclk.1700323689
Short name T224
Test name
Test status
Simulation time 19139331 ps
CPU time 0.69 seconds
Started Aug 23 06:14:14 AM UTC 24
Finished Aug 23 06:14:15 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700323689 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.1700323689
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency.3941118107
Short name T35
Test name
Test status
Simulation time 347879524 ps
CPU time 1.93 seconds
Started Aug 23 06:14:15 AM UTC 24
Finished Aug 23 06:14:18 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941118107 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.3941118107
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency_timeout.338981990
Short name T234
Test name
Test status
Simulation time 1938474421 ps
CPU time 11.23 seconds
Started Aug 23 06:14:15 AM UTC 24
Finished Aug 23 06:14:27 AM UTC 24
Peak memory 210584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338981990 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_timeout.338981990
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/7.clkmgr_idle_intersig_mubi.3963974260
Short name T227
Test name
Test status
Simulation time 27723819 ps
CPU time 0.77 seconds
Started Aug 23 06:14:18 AM UTC 24
Finished Aug 23 06:14:20 AM UTC 24
Peak memory 208088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963974260 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_idle_intersig_mubi.3963974260
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.1039361407
Short name T229
Test name
Test status
Simulation time 74202328 ps
CPU time 0.87 seconds
Started Aug 23 06:14:18 AM UTC 24
Finished Aug 23 06:14:20 AM UTC 24
Peak memory 208152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039361407
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_lc_clk_byp_req_intersig_mubi.1039361407
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.1461618961
Short name T228
Test name
Test status
Simulation time 74051562 ps
CPU time 0.89 seconds
Started Aug 23 06:14:18 AM UTC 24
Finished Aug 23 06:14:20 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461618961
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_lc_ctrl_intersig_mubi.1461618961
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/7.clkmgr_peri.734075813
Short name T226
Test name
Test status
Simulation time 28431719 ps
CPU time 0.79 seconds
Started Aug 23 06:14:16 AM UTC 24
Finished Aug 23 06:14:18 AM UTC 24
Peak memory 210212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734075813 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.734075813
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/7.clkmgr_regwen.3820228595
Short name T110
Test name
Test status
Simulation time 117499922 ps
CPU time 1.05 seconds
Started Aug 23 06:14:20 AM UTC 24
Finished Aug 23 06:14:22 AM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820228595 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.3820228595
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/7.clkmgr_smoke.3989236662
Short name T156
Test name
Test status
Simulation time 82507782 ps
CPU time 0.93 seconds
Started Aug 23 06:14:14 AM UTC 24
Finished Aug 23 06:14:16 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989236662 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.3989236662
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all.1126903832
Short name T187
Test name
Test status
Simulation time 8354770416 ps
CPU time 41.54 seconds
Started Aug 23 06:14:20 AM UTC 24
Finished Aug 23 06:15:03 AM UTC 24
Peak memory 210836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126903832 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all.1126903832
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all_with_rand_reset.1063251855
Short name T59
Test name
Test status
Simulation time 2888172234 ps
CPU time 38.34 seconds
Started Aug 23 06:14:20 AM UTC 24
Finished Aug 23 06:15:00 AM UTC 24
Peak memory 220384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063251855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.1063251855
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/7.clkmgr_trans.4019698069
Short name T225
Test name
Test status
Simulation time 19752374 ps
CPU time 0.76 seconds
Started Aug 23 06:14:16 AM UTC 24
Finished Aug 23 06:14:18 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019698069 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.4019698069
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/7.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/8.clkmgr_alert_test.1613168995
Short name T237
Test name
Test status
Simulation time 20486064 ps
CPU time 0.73 seconds
Started Aug 23 06:14:28 AM UTC 24
Finished Aug 23 06:14:29 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613168995 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_alert_test.1613168995
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.2194638270
Short name T116
Test name
Test status
Simulation time 85725550 ps
CPU time 0.96 seconds
Started Aug 23 06:14:26 AM UTC 24
Finished Aug 23 06:14:28 AM UTC 24
Peak memory 210044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194638270 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_handshake_intersig_mubi.2194638270
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_status.2151822315
Short name T115
Test name
Test status
Simulation time 43902362 ps
CPU time 0.68 seconds
Started Aug 23 06:14:24 AM UTC 24
Finished Aug 23 06:14:26 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151822315 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.2151822315
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/8.clkmgr_div_intersig_mubi.2291940381
Short name T235
Test name
Test status
Simulation time 24376762 ps
CPU time 0.76 seconds
Started Aug 23 06:14:26 AM UTC 24
Finished Aug 23 06:14:28 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291940381 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_div_intersig_mubi.2291940381
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/8.clkmgr_extclk.113354492
Short name T113
Test name
Test status
Simulation time 25003750 ps
CPU time 0.68 seconds
Started Aug 23 06:14:23 AM UTC 24
Finished Aug 23 06:14:24 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113354492 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.113354492
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency.951738213
Short name T39
Test name
Test status
Simulation time 439162913 ps
CPU time 3.57 seconds
Started Aug 23 06:14:23 AM UTC 24
Finished Aug 23 06:14:27 AM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951738213 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.951738213
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency_timeout.4110183946
Short name T246
Test name
Test status
Simulation time 1456731415 ps
CPU time 10.28 seconds
Started Aug 23 06:14:23 AM UTC 24
Finished Aug 23 06:14:34 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110183946 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_timeout.4110183946
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/8.clkmgr_idle_intersig_mubi.4141318440
Short name T230
Test name
Test status
Simulation time 33832523 ps
CPU time 0.85 seconds
Started Aug 23 06:14:24 AM UTC 24
Finished Aug 23 06:14:26 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141318440 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_idle_intersig_mubi.4141318440
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.296562209
Short name T233
Test name
Test status
Simulation time 51630167 ps
CPU time 0.75 seconds
Started Aug 23 06:14:25 AM UTC 24
Finished Aug 23 06:14:27 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296562209 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_lc_clk_byp_req_intersig_mubi.296562209
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.1527602431
Short name T232
Test name
Test status
Simulation time 24814990 ps
CPU time 0.66 seconds
Started Aug 23 06:14:25 AM UTC 24
Finished Aug 23 06:14:27 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527602431
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_lc_ctrl_intersig_mubi.1527602431
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/8.clkmgr_peri.595025525
Short name T114
Test name
Test status
Simulation time 19562630 ps
CPU time 0.68 seconds
Started Aug 23 06:14:23 AM UTC 24
Finished Aug 23 06:14:24 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595025525 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.595025525
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/8.clkmgr_regwen.3543600371
Short name T236
Test name
Test status
Simulation time 407019544 ps
CPU time 1.77 seconds
Started Aug 23 06:14:26 AM UTC 24
Finished Aug 23 06:14:29 AM UTC 24
Peak memory 209968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543600371 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.3543600371
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/8.clkmgr_smoke.3533388198
Short name T112
Test name
Test status
Simulation time 20934392 ps
CPU time 0.71 seconds
Started Aug 23 06:14:21 AM UTC 24
Finished Aug 23 06:14:23 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533388198 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.3533388198
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all.491166808
Short name T41
Test name
Test status
Simulation time 4729217129 ps
CPU time 18.72 seconds
Started Aug 23 06:14:28 AM UTC 24
Finished Aug 23 06:14:47 AM UTC 24
Peak memory 210808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491166808 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all.491166808
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all_with_rand_reset.2556780382
Short name T198
Test name
Test status
Simulation time 10513468282 ps
CPU time 73.32 seconds
Started Aug 23 06:14:28 AM UTC 24
Finished Aug 23 06:15:43 AM UTC 24
Peak memory 224384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556780382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.2556780382
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/8.clkmgr_trans.4137359065
Short name T231
Test name
Test status
Simulation time 137904380 ps
CPU time 1.19 seconds
Started Aug 23 06:14:24 AM UTC 24
Finished Aug 23 06:14:26 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137359065 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.4137359065
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/8.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/9.clkmgr_alert_test.1406190999
Short name T247
Test name
Test status
Simulation time 48397410 ps
CPU time 0.78 seconds
Started Aug 23 06:14:32 AM UTC 24
Finished Aug 23 06:14:34 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406190999 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_alert_test.1406190999
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.1996715306
Short name T117
Test name
Test status
Simulation time 31641864 ps
CPU time 0.79 seconds
Started Aug 23 06:14:31 AM UTC 24
Finished Aug 23 06:14:33 AM UTC 24
Peak memory 210044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996715306 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_handshake_intersig_mubi.1996715306
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_status.1642224504
Short name T192
Test name
Test status
Simulation time 39326501 ps
CPU time 0.7 seconds
Started Aug 23 06:14:30 AM UTC 24
Finished Aug 23 06:14:32 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642224504 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.1642224504
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/9.clkmgr_div_intersig_mubi.600467268
Short name T245
Test name
Test status
Simulation time 20895036 ps
CPU time 0.71 seconds
Started Aug 23 06:14:32 AM UTC 24
Finished Aug 23 06:14:34 AM UTC 24
Peak memory 209596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600467268 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_div_intersig_mubi.600467268
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/9.clkmgr_extclk.2534834230
Short name T239
Test name
Test status
Simulation time 27723598 ps
CPU time 0.8 seconds
Started Aug 23 06:14:28 AM UTC 24
Finished Aug 23 06:14:29 AM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534834230 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.2534834230
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency.2098548016
Short name T17
Test name
Test status
Simulation time 1280123146 ps
CPU time 9.68 seconds
Started Aug 23 06:14:29 AM UTC 24
Finished Aug 23 06:14:39 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098548016 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.2098548016
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency_timeout.1722050457
Short name T251
Test name
Test status
Simulation time 1102191118 ps
CPU time 7.67 seconds
Started Aug 23 06:14:29 AM UTC 24
Finished Aug 23 06:14:37 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722050457 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_timeout.1722050457
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/9.clkmgr_idle_intersig_mubi.1698931434
Short name T244
Test name
Test status
Simulation time 54554119 ps
CPU time 0.94 seconds
Started Aug 23 06:14:30 AM UTC 24
Finished Aug 23 06:14:32 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698931434 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_idle_intersig_mubi.1698931434
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.1691406049
Short name T242
Test name
Test status
Simulation time 16478322 ps
CPU time 0.63 seconds
Started Aug 23 06:14:30 AM UTC 24
Finished Aug 23 06:14:32 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691406049
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_lc_clk_byp_req_intersig_mubi.1691406049
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.4151519658
Short name T243
Test name
Test status
Simulation time 21215631 ps
CPU time 0.72 seconds
Started Aug 23 06:14:30 AM UTC 24
Finished Aug 23 06:14:32 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151519658
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_lc_ctrl_intersig_mubi.4151519658
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/9.clkmgr_peri.2626166136
Short name T240
Test name
Test status
Simulation time 87744928 ps
CPU time 0.8 seconds
Started Aug 23 06:14:29 AM UTC 24
Finished Aug 23 06:14:31 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626166136 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.2626166136
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/9.clkmgr_regwen.1646509381
Short name T252
Test name
Test status
Simulation time 1249481719 ps
CPU time 4.22 seconds
Started Aug 23 06:14:32 AM UTC 24
Finished Aug 23 06:14:38 AM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646509381 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.1646509381
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/9.clkmgr_smoke.1721739098
Short name T238
Test name
Test status
Simulation time 41901081 ps
CPU time 0.75 seconds
Started Aug 23 06:14:28 AM UTC 24
Finished Aug 23 06:14:29 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721739098 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.1721739098
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all.4016045221
Short name T470
Test name
Test status
Simulation time 12987741631 ps
CPU time 91.55 seconds
Started Aug 23 06:14:32 AM UTC 24
Finished Aug 23 06:16:06 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016045221 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all.4016045221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all_with_rand_reset.3466288435
Short name T82
Test name
Test status
Simulation time 2294841639 ps
CPU time 35.19 seconds
Started Aug 23 06:14:32 AM UTC 24
Finished Aug 23 06:15:09 AM UTC 24
Peak memory 224420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466288435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.3466288435
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/coverage/default/9.clkmgr_trans.3800456651
Short name T241
Test name
Test status
Simulation time 354911014 ps
CPU time 1.59 seconds
Started Aug 23 06:14:29 AM UTC 24
Finished Aug 23 06:14:31 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800456651 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.3800456651
Directory /workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/9.clkmgr_trans/latest
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