Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	204112	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

460609

1

T4

7

T5

25

T6

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	195513	1			T4	10		T5	42		T28	1
values[0x0]	223147	1			T4	9		T5	23		T6	16
values[0x1]	246061	1			T4	12		T5	16		T6	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	142828	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

521893

1

T4

10

T5

39

T6

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2164	1			T32	1		T1	1		T10	4
valid_sources[0x01]	2363	1			T5	3		T31	1		T91	1
valid_sources[0x02]	3117	1			T10	2		T212	1		T26	1
valid_sources[0x03]	2811	1			T5	1		T1	2		T62	243
valid_sources[0x04]	2808	1			T5	1		T1	1		T20	1
valid_sources[0x05]	2311	1			T5	1		T34	1		T155	1
valid_sources[0x06]	2668	1			T5	1		T31	1		T153	34
valid_sources[0x07]	2340	1			T51	1		T10	8		T208	1
valid_sources[0x08]	1986	1			T96	1		T1	1		T20	1
valid_sources[0x09]	2364	1			T10	8		T213	1		T26	1
valid_sources[0x0a]	2374	1			T31	1		T34	1		T1	1
valid_sources[0x0b]	2179	1			T28	2		T96	1		T3	5
valid_sources[0x0c]	2508	1			T1	6		T18	1		T51	1
valid_sources[0x0d]	2100	1			T208	2		T181	3		T26	2
valid_sources[0x0e]	2455	1			T21	4		T51	2		T10	1
valid_sources[0x0f]	2829	1			T34	1		T155	1		T1	1
valid_sources[0x10]	2230	1			T32	2		T155	1		T3	2
valid_sources[0x11]	2688	1			T32	2		T34	1		T133	2
valid_sources[0x12]	2703	1			T34	1		T155	1		T20	1
valid_sources[0x13]	2617	1			T5	1		T33	16		T10	12
valid_sources[0x14]	2676	1			T91	1		T10	3		T208	1
valid_sources[0x15]	2441	1			T155	1		T21	1		T10	2
valid_sources[0x16]	2387	1			T32	1		T155	1		T85	1
valid_sources[0x17]	2376	1			T34	3		T155	1		T20	2
valid_sources[0x18]	2636	1			T31	1		T34	2		T213	1
valid_sources[0x19]	2330	1			T31	1		T51	3		T10	7
valid_sources[0x1a]	2223	1			T32	1		T155	2		T156	1
valid_sources[0x1b]	1955	1			T10	1		T182	5		T26	4
valid_sources[0x1c]	2164	1			T31	1		T34	1		T85	1
valid_sources[0x1d]	2329	1			T34	1		T155	1		T10	8
valid_sources[0x1e]	2510	1			T4	1		T85	1		T96	1
valid_sources[0x1f]	2134	1			T123	1		T91	12		T179	6
valid_sources[0x20]	2456	1			T32	1		T155	1		T10	1
valid_sources[0x21]	2732	1			T31	3		T32	1		T3	2
valid_sources[0x22]	2477	1			T155	2		T1	1		T3	1
valid_sources[0x23]	2505	1			T156	1		T85	1		T21	1
valid_sources[0x24]	2850	1			T18	1		T10	9		T26	2
valid_sources[0x25]	2649	1			T20	1		T10	1		T204	1
valid_sources[0x26]	2630	1			T32	1		T34	1		T211	2
valid_sources[0x27]	2502	1			T18	1		T51	1		T10	5
valid_sources[0x28]	2715	1			T20	1		T211	4		T10	2
valid_sources[0x29]	2732	1			T93	1		T3	6		T10	2
valid_sources[0x2a]	2618	1			T32	1		T33	10		T10	7
valid_sources[0x2b]	2774	1			T1	1		T10	2		T214	1
valid_sources[0x2c]	2779	1			T5	1		T30	7		T31	1
valid_sources[0x2d]	2417	1			T155	2		T179	4		T208	1
valid_sources[0x2e]	2405	1			T155	1		T26	2		T71	3
valid_sources[0x2f]	2599	1			T30	3		T93	2		T10	1
valid_sources[0x30]	2372	1			T123	1		T10	4		T212	2
valid_sources[0x31]	2712	1			T31	1		T86	4		T1	2
valid_sources[0x32]	2490	1			T31	1		T34	1		T1	1
valid_sources[0x33]	2320	1			T32	1		T133	2		T20	1
valid_sources[0x34]	2135	1			T31	1		T10	1		T182	2
valid_sources[0x35]	2517	1			T155	1		T1	1		T18	1
valid_sources[0x36]	2322	1			T32	1		T96	1		T21	1
valid_sources[0x37]	2724	1			T155	1		T156	1		T51	1
valid_sources[0x38]	2865	1			T93	2		T1	1		T213	1
valid_sources[0x39]	2334	1			T5	1		T30	10		T32	1
valid_sources[0x3a]	2288	1			T5	1		T156	2		T92	3
valid_sources[0x3b]	2319	1			T28	1		T32	1		T133	1
valid_sources[0x3c]	2125	1			T10	2		T26	2		T71	1
valid_sources[0x3d]	2522	1			T78	7		T51	2		T10	6
valid_sources[0x3e]	2061	1			T5	2		T31	1		T20	1
valid_sources[0x3f]	2889	1			T32	1		T34	1		T95	2
valid_sources[0x40]	2903	1			T5	2		T133	2		T123	1
valid_sources[0x41]	2483	1			T156	2		T21	1		T10	15
valid_sources[0x42]	2448	1			T31	1		T179	4		T1	1
valid_sources[0x43]	2717	1			T156	2		T1	1		T10	1
valid_sources[0x44]	2316	1			T20	1		T51	2		T10	7
valid_sources[0x45]	2359	1			T85	1		T10	8		T81	1
valid_sources[0x46]	2491	1			T4	3		T32	1		T18	1
valid_sources[0x47]	2428	1			T32	1		T158	91		T1	1
valid_sources[0x48]	2296	1			T5	2		T31	1		T18	1
valid_sources[0x49]	2314	1			T155	1		T203	1		T204	2
valid_sources[0x4a]	2670	1			T5	4		T34	1		T86	2
valid_sources[0x4b]	2613	1			T5	1		T31	1		T34	1
valid_sources[0x4c]	2948	1			T31	2		T123	2		T10	3
valid_sources[0x4d]	2645	1			T18	1		T10	12		T208	1
valid_sources[0x4e]	2429	1			T133	1		T214	1		T213	1
valid_sources[0x4f]	3381	1			T84	11		T1	1		T10	1
valid_sources[0x50]	2356	1			T21	1		T10	5		T81	2
valid_sources[0x51]	2103	1			T21	5		T51	2		T10	4
valid_sources[0x52]	2737	1			T5	1		T34	1		T3	3
valid_sources[0x53]	2780	1			T34	1		T18	1		T10	9
valid_sources[0x54]	2235	1			T1	1		T97	2		T10	1
valid_sources[0x55]	2837	1			T155	1		T180	14		T26	2
valid_sources[0x56]	2448	1			T18	1		T81	1		T26	5
valid_sources[0x57]	2688	1			T5	1		T156	3		T10	3
valid_sources[0x58]	2477	1			T78	16		T51	1		T10	1
valid_sources[0x59]	2200	1			T156	1		T93	1		T1	3
valid_sources[0x5a]	2241	1			T5	2		T34	2		T20	1
valid_sources[0x5b]	3235	1			T5	3		T51	3		T211	1
valid_sources[0x5c]	2500	1			T34	1		T133	3		T134	25
valid_sources[0x5d]	2363	1			T31	1		T32	1		T155	1
valid_sources[0x5e]	3119	1			T31	1		T32	1		T20	1
valid_sources[0x5f]	2336	1			T4	7		T34	1		T26	1
valid_sources[0x60]	5581	1			T156	1		T78	3		T91	1
valid_sources[0x61]	2416	1			T28	1		T30	6		T156	1
valid_sources[0x62]	2848	1			T31	1		T84	3		T18	1
valid_sources[0x63]	2263	1			T5	1		T1	2		T18	1
valid_sources[0x64]	2565	1			T156	1		T96	1		T211	5
valid_sources[0x65]	2581	1			T31	1		T20	1		T51	3
valid_sources[0x66]	2694	1			T155	1		T26	1		T68	1
valid_sources[0x67]	2303	1			T32	2		T34	1		T1	1
valid_sources[0x68]	2677	1			T32	1		T20	1		T10	1
valid_sources[0x69]	4810	1			T156	1		T18	1		T10	4
valid_sources[0x6a]	2757	1			T32	1		T18	2		T81	1
valid_sources[0x6b]	2684	1			T31	1		T123	1		T18	1
valid_sources[0x6c]	2434	1			T34	1		T18	1		T21	1
valid_sources[0x6d]	2631	1			T18	1		T26	4		T71	1
valid_sources[0x6e]	2808	1			T5	3		T123	2		T20	1
valid_sources[0x6f]	2579	1			T21	1		T51	2		T10	6
valid_sources[0x70]	2552	1			T5	2		T1	2		T18	3
valid_sources[0x71]	2688	1			T5	1		T93	2		T1	1
valid_sources[0x72]	2273	1			T155	1		T156	1		T211	3
valid_sources[0x73]	2539	1			T5	1		T30	2		T95	1
valid_sources[0x74]	2804	1			T85	1		T1	2		T10	1
valid_sources[0x75]	2093	1			T5	3		T34	2		T1	1
valid_sources[0x76]	2653	1			T5	2		T32	2		T96	2
valid_sources[0x77]	2372	1			T5	1		T51	1		T203	1
valid_sources[0x78]	2533	1			T93	1		T10	4		T208	1
valid_sources[0x79]	2983	1			T6	39		T123	1		T10	4
valid_sources[0x7a]	2608	1			T5	1		T20	2		T10	9
valid_sources[0x7b]	2560	1			T1	1		T20	1		T21	3
valid_sources[0x7c]	2386	1			T10	1		T8	1		T65	1
valid_sources[0x7d]	2539	1			T31	1		T96	1		T10	3
valid_sources[0x7e]	2718	1			T34	1		T84	5		T10	6
valid_sources[0x7f]	2954	1			T20	1		T10	5		T212	3
valid_sources[0x80]	2497	1			T5	5		T31	1		T1	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

129371

1

T5

17

T30

13

T31

6

values[0x0]

all_enables

biggest_size

178222

1

T4

5

T5

7

T6

3

values[0x1]

all_enables

biggest_size

153016

1

T4

2

T5

1

T6

2