Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T29
0	1	Covered	T6,T133,T91
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T82
1	0	Covered	T29,T79,T80
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	186894763	8277	0	0
GateOpen_A	186894763	14869	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186894763	8277	0	0
T5	15171	4	0	0
T6	17301	35	0	0
T28	2822	0	0	0
T29	8620	12	0	0
T30	10688	0	0	0
T31	6366	0	0	0
T32	9228	0	0	0
T33	13477	0	0	0
T34	5809	0	0	0
T79	0	7	0	0
T80	0	12	0	0
T82	4211	4	0	0
T83	0	3	0	0
T91	0	27	0	0
T92	0	10	0	0
T94	0	5	0	0
T133	0	22	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186894763	14869	0	0
T4	12395	4	0	0
T5	15171	4	0	0
T6	17301	39	0	0
T28	2822	0	0	0
T29	8620	16	0	0
T30	10688	0	0	0
T31	6366	0	0	0
T32	9228	4	0	0
T33	13477	0	0	0
T34	5809	0	0	0
T79	0	11	0	0
T80	0	16	0	0
T82	0	8	0	0
T84	0	4	0	0
T133	0	26	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T29
0	1	Covered	T6,T133,T91
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T82
1	0	Covered	T29,T79,T80
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	20166791	1971	0	0
GateOpen_A	20166791	3616	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20166791	1971	0	0
T5	1666	1	0	0
T6	1914	8	0	0
T28	301	0	0	0
T29	938	3	0	0
T30	1168	0	0	0
T31	717	0	0	0
T32	1399	0	0	0
T33	1487	0	0	0
T34	696	0	0	0
T79	0	2	0	0
T80	0	3	0	0
T82	448	1	0	0
T91	0	6	0	0
T92	0	2	0	0
T94	0	5	0	0
T133	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20166791	3616	0	0
T4	1491	1	0	0
T5	1666	1	0	0
T6	1914	9	0	0
T28	301	0	0	0
T29	938	4	0	0
T30	1168	0	0	0
T31	717	0	0	0
T32	1399	1	0	0
T33	1487	0	0	0
T34	696	0	0	0
T79	0	3	0	0
T80	0	4	0	0
T82	0	2	0	0
T84	0	1	0	0
T133	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T29
0	1	Covered	T6,T133,T91
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T82
1	0	Covered	T29,T79,T80
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	40333983	2114	0	0
GateOpen_A	40333983	3759	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40333983	2114	0	0
T5	3331	1	0	0
T6	3827	10	0	0
T28	601	0	0	0
T29	1876	3	0	0
T30	2335	0	0	0
T31	1437	0	0	0
T32	2799	0	0	0
T33	2973	0	0	0
T34	1393	0	0	0
T79	0	2	0	0
T80	0	3	0	0
T82	896	1	0	0
T83	0	1	0	0
T91	0	7	0	0
T92	0	3	0	0
T133	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40333983	3759	0	0
T4	2983	1	0	0
T5	3331	1	0	0
T6	3827	11	0	0
T28	601	0	0	0
T29	1876	4	0	0
T30	2335	0	0	0
T31	1437	0	0	0
T32	2799	1	0	0
T33	2973	0	0	0
T34	1393	0	0	0
T79	0	3	0	0
T80	0	4	0	0
T82	0	2	0	0
T84	0	1	0	0
T133	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T29
0	1	Covered	T6,T133,T91
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T82
1	0	Covered	T29,T79,T80
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	82648703	2112	0	0
GateOpen_A	82648703	3763	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82648703	2112	0	0
T5	6782	1	0	0
T6	7707	9	0	0
T28	1280	0	0	0
T29	3858	3	0	0
T30	4790	0	0	0
T31	2808	0	0	0
T32	3353	0	0	0
T33	6011	0	0	0
T34	2480	0	0	0
T79	0	2	0	0
T80	0	3	0	0
T82	1912	1	0	0
T83	0	1	0	0
T91	0	8	0	0
T92	0	3	0	0
T133	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82648703	3763	0	0
T4	5280	1	0	0
T5	6782	1	0	0
T6	7707	10	0	0
T28	1280	0	0	0
T29	3858	4	0	0
T30	4790	0	0	0
T31	2808	0	0	0
T32	3353	1	0	0
T33	6011	0	0	0
T34	2480	0	0	0
T79	0	3	0	0
T80	0	4	0	0
T82	0	2	0	0
T84	0	1	0	0
T133	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T29
0	1	Covered	T6,T133,T91
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T82
1	0	Covered	T29,T79,T80
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	43745286	2080	0	0
GateOpen_A	43745286	3731	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43745286	2080	0	0
T5	3392	1	0	0
T6	3853	8	0	0
T28	640	0	0	0
T29	1948	3	0	0
T30	2395	0	0	0
T31	1404	0	0	0
T32	1677	0	0	0
T33	3006	0	0	0
T34	1240	0	0	0
T79	0	1	0	0
T80	0	3	0	0
T82	955	1	0	0
T83	0	1	0	0
T91	0	6	0	0
T92	0	2	0	0
T133	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43745286	3731	0	0
T4	2641	1	0	0
T5	3392	1	0	0
T6	3853	9	0	0
T28	640	0	0	0
T29	1948	4	0	0
T30	2395	0	0	0
T31	1404	0	0	0
T32	1677	1	0	0
T33	3006	0	0	0
T34	1240	0	0	0
T79	0	2	0	0
T80	0	4	0	0
T82	0	2	0	0
T84	0	1	0	0
T133	0	6	0	0