Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	190083615	32270	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	190083615	32270	0	0
T1	212340	92	0	0
T2	231865	0	0	0
T8	0	216	0	0
T9	0	76	0	0
T11	0	72	0	0
T12	0	209	0	0
T13	0	57	0	0
T14	0	246	0	0
T15	0	95	0	0
T16	0	86	0	0
T17	0	198	0	0
T18	9450	0	0	0
T19	16010	0	0	0
T20	10340	0	0	0
T21	83655	0	0	0
T22	8595	0	0	0
T23	8905	0	0	0
T24	11405	0	0	0
T25	4510	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38016723	4797	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	4797	0	0
T1	42468	13	0	0
T2	46373	0	0	0
T8	0	28	0	0
T9	0	11	0	0
T11	0	10	0	0
T12	0	34	0	0
T13	0	8	0	0
T14	0	32	0	0
T15	0	12	0	0
T16	0	14	0	0
T17	0	29	0	0
T18	1890	0	0	0
T19	3202	0	0	0
T20	2068	0	0	0
T21	16731	0	0	0
T22	1719	0	0	0
T23	1781	0	0	0
T24	2281	0	0	0
T25	902	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38016723	4709	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	4709	0	0
T1	42468	11	0	0
T2	46373	0	0	0
T8	0	31	0	0
T9	0	11	0	0
T11	0	10	0	0
T12	0	34	0	0
T13	0	8	0	0
T14	0	33	0	0
T15	0	14	0	0
T16	0	14	0	0
T17	0	24	0	0
T18	1890	0	0	0
T19	3202	0	0	0
T20	2068	0	0	0
T21	16731	0	0	0
T22	1719	0	0	0
T23	1781	0	0	0
T24	2281	0	0	0
T25	902	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38016723	6482	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	6482	0	0
T1	42468	18	0	0
T2	46373	0	0	0
T8	0	43	0	0
T9	0	17	0	0
T11	0	16	0	0
T12	0	42	0	0
T13	0	13	0	0
T14	0	49	0	0
T15	0	19	0	0
T16	0	18	0	0
T17	0	39	0	0
T18	1890	0	0	0
T19	3202	0	0	0
T20	2068	0	0	0
T21	16731	0	0	0
T22	1719	0	0	0
T23	1781	0	0	0
T24	2281	0	0	0
T25	902	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38016723	6475	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	6475	0	0
T1	42468	19	0	0
T2	46373	0	0	0
T8	0	44	0	0
T9	0	15	0	0
T11	0	14	0	0
T12	0	42	0	0
T13	0	11	0	0
T14	0	48	0	0
T15	0	19	0	0
T16	0	18	0	0
T17	0	40	0	0
T18	1890	0	0	0
T19	3202	0	0	0
T20	2068	0	0	0
T21	16731	0	0	0
T22	1719	0	0	0
T23	1781	0	0	0
T24	2281	0	0	0
T25	902	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38016723	9807	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	9807	0	0
T1	42468	31	0	0
T2	46373	0	0	0
T8	0	70	0	0
T9	0	22	0	0
T11	0	22	0	0
T12	0	57	0	0
T13	0	17	0	0
T14	0	84	0	0
T15	0	31	0	0
T16	0	22	0	0
T17	0	66	0	0
T18	1890	0	0	0
T19	3202	0	0	0
T20	2068	0	0	0
T21	16731	0	0	0
T22	1719	0	0	0
T23	1781	0	0	0
T24	2281	0	0	0
T25	902	0	0	0