Module Definition
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Module : clkmgr_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.57 100.00 98.30 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_clkmgr_reg_0.1/rtl/clkmgr_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.64 98.39 95.42 100.00 97.91 96.48


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_test_fatal_fault 100.00 100.00
u_alert_test_recov_fault 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_clk_enables_clk_io_div2_peri_en 100.00 100.00 100.00 100.00
u_clk_enables_clk_io_div4_peri_en 100.00 100.00 100.00 100.00
u_clk_enables_clk_io_peri_en 100.00 100.00 100.00 100.00
u_clk_enables_clk_usb_peri_en 100.00 100.00 100.00 100.00
u_clk_hints_clk_main_aes_hint 100.00 100.00 100.00 100.00
u_clk_hints_clk_main_hmac_hint 100.00 100.00 100.00 100.00
u_clk_hints_clk_main_kmac_hint 100.00 100.00 100.00 100.00
u_clk_hints_clk_main_otbn_hint 100.00 100.00 100.00 100.00
u_clk_hints_status_clk_main_aes_val 92.59 77.78 100.00 100.00
u_clk_hints_status_clk_main_hmac_val 92.59 77.78 100.00 100.00
u_clk_hints_status_clk_main_kmac_val 92.59 77.78 100.00 100.00
u_clk_hints_status_clk_main_otbn_val 92.59 77.78 100.00 100.00
u_extclk_ctrl_hi_speed_sel 100.00 100.00 100.00 100.00
u_extclk_ctrl_regwen 100.00 100.00 100.00 100.00
u_extclk_ctrl_sel 100.00 100.00 100.00 100.00
u_extclk_status 100.00 100.00
u_fatal_err_code_idle_cnt 96.30 88.89 100.00 100.00
u_fatal_err_code_reg_intg 96.30 88.89 100.00 100.00
u_fatal_err_code_shadow_storage_err 96.30 88.89 100.00 100.00
u_io_div2_meas_ctrl_en 100.00 100.00 100.00 100.00
u_io_div2_meas_ctrl_en_cdc 89.66 96.24 80.88 91.53 90.00
u_io_div2_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_io_div2_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_io_div2_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_div2_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_io_div2_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_div4_meas_ctrl_en 100.00 100.00 100.00 100.00
u_io_div4_meas_ctrl_en_cdc 92.36 97.74 86.76 94.92 90.00
u_io_div4_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_io_div4_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_io_div4_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_div4_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_io_div4_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_meas_ctrl_en 100.00 100.00 100.00 100.00
u_io_meas_ctrl_en_cdc 89.66 96.24 80.88 91.53 90.00
u_io_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_io_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_io_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_io_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_io_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_io_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_io_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_jitter_enable 100.00 100.00 100.00 100.00
u_jitter_regwen 100.00 100.00 100.00 100.00
u_main_meas_ctrl_en 100.00 100.00 100.00 100.00
u_main_meas_ctrl_en_cdc 89.66 96.24 80.88 91.53 90.00
u_main_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_main_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_main_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_main_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_main_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_main_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_main_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_measure_ctrl_regwen 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_recov_err_code_io_div2_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_div2_timeout_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_div4_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_div4_timeout_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_io_timeout_err 100.00 100.00 100.00 100.00
u_recov_err_code_main_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_main_timeout_err 100.00 100.00 100.00 100.00
u_recov_err_code_shadow_update_err 97.22 100.00 91.67 100.00
u_recov_err_code_usb_measure_err 100.00 100.00 100.00 100.00
u_recov_err_code_usb_timeout_err 100.00 100.00 100.00 100.00
u_reg_if 98.98 97.14 98.80 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_usb_meas_ctrl_en 100.00 100.00 100.00 100.00
u_usb_meas_ctrl_en_cdc 89.66 96.24 80.88 91.53 90.00
u_usb_meas_ctrl_shadowed_cdc 98.39 100.00 93.55 100.00 100.00
u_usb_meas_ctrl_shadowed_hi 99.55 100.00 98.21 100.00 100.00
u_usb_meas_ctrl_shadowed_hi_err_storage_sync 100.00 100.00 100.00
u_usb_meas_ctrl_shadowed_hi_err_update_sync 100.00 100.00 100.00 100.00 100.00
u_usb_meas_ctrl_shadowed_lo 99.55 100.00 98.21 100.00 100.00
u_usb_meas_ctrl_shadowed_lo_err_storage_sync 100.00 100.00 100.00
u_usb_meas_ctrl_shadowed_lo_err_update_sync 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : clkmgr_reg_top
Line No.TotalCoveredPercent
TOTAL244244100.00
ALWAYS8244100.00
CONT_ASSIGN9111100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
ALWAYS27744100.00
CONT_ASSIGN30711100.00
ALWAYS32033100.00
CONT_ASSIGN34911100.00
ALWAYS36344100.00
CONT_ASSIGN39311100.00
ALWAYS40633100.00
CONT_ASSIGN43511100.00
ALWAYS44944100.00
CONT_ASSIGN47911100.00
ALWAYS49233100.00
CONT_ASSIGN52111100.00
ALWAYS53544100.00
CONT_ASSIGN56511100.00
ALWAYS57833100.00
CONT_ASSIGN60711100.00
ALWAYS62144100.00
CONT_ASSIGN65111100.00
ALWAYS66433100.00
CONT_ASSIGN69311100.00
CONT_ASSIGN70011100.00
CONT_ASSIGN71511100.00
CONT_ASSIGN73111100.00
CONT_ASSIGN76511100.00
CONT_ASSIGN125311100.00
CONT_ASSIGN125611100.00
CONT_ASSIGN128711100.00
CONT_ASSIGN141011100.00
CONT_ASSIGN141311100.00
CONT_ASSIGN144511100.00
CONT_ASSIGN156811100.00
CONT_ASSIGN157111100.00
CONT_ASSIGN160311100.00
CONT_ASSIGN172611100.00
CONT_ASSIGN172911100.00
CONT_ASSIGN176111100.00
CONT_ASSIGN188411100.00
CONT_ASSIGN188711100.00
CONT_ASSIGN191811100.00
ALWAYS24242323100.00
CONT_ASSIGN244911100.00
ALWAYS245311100.00
CONT_ASSIGN247911100.00
CONT_ASSIGN248111100.00
CONT_ASSIGN248311100.00
CONT_ASSIGN248411100.00
CONT_ASSIGN248611100.00
CONT_ASSIGN248711100.00
CONT_ASSIGN248911100.00
CONT_ASSIGN249111100.00
CONT_ASSIGN249211100.00
CONT_ASSIGN249311100.00
CONT_ASSIGN249511100.00
CONT_ASSIGN249611100.00
CONT_ASSIGN249811100.00
CONT_ASSIGN249911100.00
CONT_ASSIGN250111100.00
CONT_ASSIGN250311100.00
CONT_ASSIGN250511100.00
CONT_ASSIGN250711100.00
CONT_ASSIGN250811100.00
CONT_ASSIGN251011100.00
CONT_ASSIGN251211100.00
CONT_ASSIGN251411100.00
CONT_ASSIGN251611100.00
CONT_ASSIGN251711100.00
CONT_ASSIGN251911100.00
CONT_ASSIGN252011100.00
CONT_ASSIGN252211100.00
CONT_ASSIGN252311100.00
CONT_ASSIGN252611100.00
CONT_ASSIGN252811100.00
CONT_ASSIGN252911100.00
CONT_ASSIGN253211100.00
CONT_ASSIGN253411100.00
CONT_ASSIGN253511100.00
CONT_ASSIGN253811100.00
CONT_ASSIGN254011100.00
CONT_ASSIGN254111100.00
CONT_ASSIGN254411100.00
CONT_ASSIGN254611100.00
CONT_ASSIGN254711100.00
CONT_ASSIGN255011100.00
CONT_ASSIGN255211100.00
CONT_ASSIGN255411100.00
CONT_ASSIGN255611100.00
CONT_ASSIGN255811100.00
CONT_ASSIGN256011100.00
CONT_ASSIGN256211100.00
CONT_ASSIGN256411100.00
CONT_ASSIGN256611100.00
CONT_ASSIGN256811100.00
CONT_ASSIGN257011100.00
CONT_ASSIGN257211100.00
ALWAYS25762323100.00
ALWAYS26034747100.00
ALWAYS271733100.00
ALWAYS272533100.00
CONT_ASSIGN273311100.00
CONT_ASSIGN273611100.00
CONT_ASSIGN274811100.00
CONT_ASSIGN276311100.00
ALWAYS27651212100.00
CONT_ASSIGN281011100.00
CONT_ASSIGN281111100.00

Click here to see the source line report.
Cond Coverage for Module : clkmgr_reg_top
TotalCoveredPercent
Conditions29428998.30
Logical29428998.30
Non-Logical00
Event00

 LINE       72
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T40,T90
11CoveredT4,T5,T6 

 LINE       84
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT78,T21,T81
10CoveredT141,T142,T143 

 LINE       91
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT78,T21,T81
010CoveredT141,T142,T143
100CoveredT78,T21,T81 

 LINE       133
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT141,T142,T143
010CoveredT36,T40,T90
100CoveredT36,T40,T90 

 LINE       765
 EXPRESSION (extclk_ctrl_we & extclk_ctrl_regwen_qs)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT2,T10,T27
11CoveredT4,T28,T31 

 LINE       1256
 EXPRESSION (io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen)
             ----------1----------   ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1287
 EXPRESSION (io_io_meas_ctrl_shadowed_we & io_io_meas_ctrl_shadowed_regwen)
             -------------1-------------   ---------------2---------------
-1--2-StatusTests
01CoveredT2,T10,T27
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1413
 EXPRESSION (io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1445
 EXPRESSION (io_div2_io_div2_meas_ctrl_shadowed_we & io_div2_io_div2_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT2,T10,T27
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1571
 EXPRESSION (io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1603
 EXPRESSION (io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT2,T10,T27
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1729
 EXPRESSION (main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen)
             ------------1------------   --------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1761
 EXPRESSION (main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTests
01CoveredT2,T10,T27
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1887
 EXPRESSION (usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen)
             -----------1-----------   -------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1918
 EXPRESSION (usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen)
             --------------1--------------   ----------------2----------------
-1--2-StatusTests
01CoveredT2,T10,T27
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       2425
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T32,T84 

 LINE       2426
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T28 

 LINE       2427
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       2428
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_STATUS_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T32 

 LINE       2429
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_REGWEN_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T1,T2 

 LINE       2430
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_ENABLE_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T32 

 LINE       2431
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_ENABLES_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T82 

 LINE       2432
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_OFFSET)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T30,T33 

 LINE       2433
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_STATUS_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T30 

 LINE       2434
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MEASURE_CTRL_REGWEN_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T133 

 LINE       2435
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_EN_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T32 

 LINE       2436
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T133 

 LINE       2437
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T32,T133 

 LINE       2438
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T32 

 LINE       2439
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T1 

 LINE       2440
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T32 

 LINE       2441
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET)
            ------------------------------1------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T133 

 LINE       2442
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T32 

 LINE       2443
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_EN_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T1 

 LINE       2444
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T133 

 LINE       2445
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_RECOV_ERR_CODE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T32 

 LINE       2446
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_FATAL_ERR_CODE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T32 

 LINE       2449
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       2449
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T28 

 LINE       2453
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT36,T40,T90 

 LINE       2453
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT4,T5,T6
22 (addr_hit[21] & ((|(4'...CoveredT6,T85,T1
21 (addr_hit[20] & ((|(4'...CoveredT5,T6,T32
20 (addr_hit[19] & ((|(4'...CoveredT5,T6,T133
19 (addr_hit[18] & ((|(4'...CoveredT5,T1,T2
18 (addr_hit[17] & ((|(4'...CoveredT5,T6,T32
17 (addr_hit[16] & ((|(4'...CoveredT5,T6,T133
16 (addr_hit[15] & ((|(4'...CoveredT5,T133,T1
15 (addr_hit[14] & ((|(4'...CoveredT5,T1,T23
14 (addr_hit[13] & ((|(4'...CoveredT5,T6,T32
13 (addr_hit[12] & ((|(4'...CoveredT32,T133,T1
12 (addr_hit[11] & ((|(4'...CoveredT5,T6,T133
11 (addr_hit[10] & ((|(4'...CoveredT5,T6,T32
10 (addr_hit[9] & ((|(4'b...CoveredT5,T1,T2
9 (addr_hit[8] & ((|(4'b...CoveredT5,T6,T30
8 (addr_hit[7] & ((|(4'b...CoveredT5,T85,T1
7 (addr_hit[6] & ((|(4'b...CoveredT6,T82,T133
6 (addr_hit[5] & ((|(4'b...CoveredT5,T6,T82
5 (addr_hit[4] & ((|(4'b...CoveredT5,T1,T2
4 (addr_hit[3] & ((|(4'b...CoveredT5,T6,T32
3 (addr_hit[2] & ((|(4'b...CoveredT4,T5,T28
2 (addr_hit[1] & ((|(4'b...CoveredT5,T133,T1
1 (addr_hit[0] & ((|(4'b...CoveredT5,T133,T2 

 LINE       2453
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T32,T84
11CoveredT5,T133,T2 

 LINE       2453
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T28
11CoveredT5,T133,T1 

 LINE       2453
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT5,T6,T30
10CoveredT4,T6,T28
11CoveredT4,T5,T28 

 LINE       2453
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T32
11CoveredT5,T6,T32 

 LINE       2453
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T27
11CoveredT5,T1,T2 

 LINE       2453
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T32,T82
11CoveredT5,T6,T82 

 LINE       2453
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T82
11CoveredT6,T82,T133 

 LINE       2453
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T30,T33
11CoveredT5,T85,T1 

 LINE       2453
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T30,T33
11CoveredT5,T6,T30 

 LINE       2453
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T133
11CoveredT5,T1,T2 

 LINE       2453
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T85
11CoveredT5,T6,T32 

 LINE       2453
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT5,T6,T133 

 LINE       2453
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T32,T133
11CoveredT32,T133,T1 

 LINE       2453
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT32,T1,T2
11CoveredT5,T6,T32 

 LINE       2453
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T1
11CoveredT5,T1,T23 

 LINE       2453
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T32,T1
11CoveredT5,T133,T1 

 LINE       2453
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T1,T2
11CoveredT5,T6,T133 

 LINE       2453
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT32,T1,T2
11CoveredT5,T6,T32 

 LINE       2453
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T1
11CoveredT5,T1,T2 

 LINE       2453
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT85,T1,T2
11CoveredT5,T6,T133 

 LINE       2453
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT32,T1,T2
11CoveredT5,T6,T32 

 LINE       2453
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T32
11CoveredT6,T85,T1 

 LINE       2479
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T32,T84
110CoveredT36,T40,T90
111CoveredT84,T85,T86 

 LINE       2484
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT4,T5,T28
110CoveredT36,T40,T90
111CoveredT4,T28,T31 

 LINE       2487
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT4,T5,T6
110CoveredT36,T40,T90
111CoveredT4,T28,T31 

 LINE       2492
 EXPRESSION (addr_hit[3] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T28
101CoveredT5,T6,T32
110CoveredT144,T145
111CoveredT32,T123,T20 

 LINE       2493
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T1,T2
110CoveredT36,T40,T90
111CoveredT146,T127,T128 

 LINE       2496
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T32
110CoveredT36,T40,T90
111CoveredT5,T82,T83 

 LINE       2499
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T28
101CoveredT5,T6,T82
110CoveredT36,T40,T90
111CoveredT5,T6,T82 

 LINE       2508
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T30,T33
110CoveredT36,T40,T90
111CoveredT5,T30,T33 

 LINE       2517
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T133
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2520
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T32
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2522
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T28
101CoveredT5,T6,T79
110CoveredT144
111CoveredT2,T10,T27 

 LINE       2523
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T79
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2526
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T32,T133
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2528
 EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T28
101CoveredT5,T6,T32
110CoveredT147,T144,T148
111CoveredT2,T10,T27 

 LINE       2529
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T32
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2532
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T1
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2534
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T28
101CoveredT5,T6,T32
110CoveredT149,T150,T151
111CoveredT2,T10,T27 

 LINE       2535
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T32
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2538
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T133
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2540
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T28
101CoveredT5,T6,T32
110CoveredT142,T145
111CoveredT2,T10,T27 

 LINE       2541
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T32
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2544
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T1
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2546
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T28
101CoveredT5,T6,T133
110CoveredT152
111CoveredT2,T10,T27 

 LINE       2547
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T133
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2550
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T32
110CoveredT36,T40,T90
111CoveredT1,T3,T51 

 LINE       2733
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------
-1--2-StatusTests
01CoveredT100,T102,T101
10CoveredT10,T27,T26
11CoveredT4,T5,T6 

 LINE       2763
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT5,T6,T32
10CoveredT1,T2,T3
Branch Coverage for Module : clkmgr_reg_top
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 2449 2 2 100.00
IF 82 3 3 100.00
CASE 2604 23 23 100.00
IF 2717 2 2 100.00
IF 2725 2 2 100.00
CASE 2766 11 11 100.00 



2449         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



82             if (!rst_ni) begin
               -1-  
83               err_q <= '0;
                 ==>
84             end else if (intg_err || reg_we_err) begin
                        -2-  
85               err_q <= 1'b1;
                 ==>
86             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T78,T21,T81
0 0 Covered T4,T5,T6 



2604           unique case (1'b1)
                      -1-  
2605             addr_hit[0]: begin
2606               reg_rdata_next[0] = '0;
                   ==>
2607               reg_rdata_next[1] = '0;
2608             end
2609       
2610             addr_hit[1]: begin
2611               reg_rdata_next[0] = extclk_ctrl_regwen_qs;
                   ==>
2612             end
2613       
2614             addr_hit[2]: begin
2615               reg_rdata_next[3:0] = extclk_ctrl_sel_qs;
                   ==>
2616               reg_rdata_next[7:4] = extclk_ctrl_hi_speed_sel_qs;
2617             end
2618       
2619             addr_hit[3]: begin
2620               reg_rdata_next[3:0] = extclk_status_qs;
                   ==>
2621             end
2622       
2623             addr_hit[4]: begin
2624               reg_rdata_next[0] = jitter_regwen_qs;
                   ==>
2625             end
2626       
2627             addr_hit[5]: begin
2628               reg_rdata_next[3:0] = jitter_enable_qs;
                   ==>
2629             end
2630       
2631             addr_hit[6]: begin
2632               reg_rdata_next[0] = clk_enables_clk_io_div4_peri_en_qs;
                   ==>
2633               reg_rdata_next[1] = clk_enables_clk_io_div2_peri_en_qs;
2634               reg_rdata_next[2] = clk_enables_clk_io_peri_en_qs;
2635               reg_rdata_next[3] = clk_enables_clk_usb_peri_en_qs;
2636             end
2637       
2638             addr_hit[7]: begin
2639               reg_rdata_next[0] = clk_hints_clk_main_aes_hint_qs;
                   ==>
2640               reg_rdata_next[1] = clk_hints_clk_main_hmac_hint_qs;
2641               reg_rdata_next[2] = clk_hints_clk_main_kmac_hint_qs;
2642               reg_rdata_next[3] = clk_hints_clk_main_otbn_hint_qs;
2643             end
2644       
2645             addr_hit[8]: begin
2646               reg_rdata_next[0] = clk_hints_status_clk_main_aes_val_qs;
                   ==>
2647               reg_rdata_next[1] = clk_hints_status_clk_main_hmac_val_qs;
2648               reg_rdata_next[2] = clk_hints_status_clk_main_kmac_val_qs;
2649               reg_rdata_next[3] = clk_hints_status_clk_main_otbn_val_qs;
2650             end
2651       
2652             addr_hit[9]: begin
2653               reg_rdata_next[0] = measure_ctrl_regwen_qs;
                   ==>
2654             end
2655       
2656             addr_hit[10]: begin
2657               reg_rdata_next = DW'(io_meas_ctrl_en_qs);
                   ==>
2658             end
2659             addr_hit[11]: begin
2660               reg_rdata_next = DW'(io_meas_ctrl_shadowed_qs);
                   ==>
2661             end
2662             addr_hit[12]: begin
2663               reg_rdata_next = DW'(io_div2_meas_ctrl_en_qs);
                   ==>
2664             end
2665             addr_hit[13]: begin
2666               reg_rdata_next = DW'(io_div2_meas_ctrl_shadowed_qs);
                   ==>
2667             end
2668             addr_hit[14]: begin
2669               reg_rdata_next = DW'(io_div4_meas_ctrl_en_qs);
                   ==>
2670             end
2671             addr_hit[15]: begin
2672               reg_rdata_next = DW'(io_div4_meas_ctrl_shadowed_qs);
                   ==>
2673             end
2674             addr_hit[16]: begin
2675               reg_rdata_next = DW'(main_meas_ctrl_en_qs);
                   ==>
2676             end
2677             addr_hit[17]: begin
2678               reg_rdata_next = DW'(main_meas_ctrl_shadowed_qs);
                   ==>
2679             end
2680             addr_hit[18]: begin
2681               reg_rdata_next = DW'(usb_meas_ctrl_en_qs);
                   ==>
2682             end
2683             addr_hit[19]: begin
2684               reg_rdata_next = DW'(usb_meas_ctrl_shadowed_qs);
                   ==>
2685             end
2686             addr_hit[20]: begin
2687               reg_rdata_next[0] = recov_err_code_shadow_update_err_qs;
                   ==>
2688               reg_rdata_next[1] = recov_err_code_io_measure_err_qs;
2689               reg_rdata_next[2] = recov_err_code_io_div2_measure_err_qs;
2690               reg_rdata_next[3] = recov_err_code_io_div4_measure_err_qs;
2691               reg_rdata_next[4] = recov_err_code_main_measure_err_qs;
2692               reg_rdata_next[5] = recov_err_code_usb_measure_err_qs;
2693               reg_rdata_next[6] = recov_err_code_io_timeout_err_qs;
2694               reg_rdata_next[7] = recov_err_code_io_div2_timeout_err_qs;
2695               reg_rdata_next[8] = recov_err_code_io_div4_timeout_err_qs;
2696               reg_rdata_next[9] = recov_err_code_main_timeout_err_qs;
2697               reg_rdata_next[10] = recov_err_code_usb_timeout_err_qs;
2698             end
2699       
2700             addr_hit[21]: begin
2701               reg_rdata_next[0] = fatal_err_code_reg_intg_qs;
                   ==>
2702               reg_rdata_next[1] = fatal_err_code_idle_cnt_qs;
2703               reg_rdata_next[2] = fatal_err_code_shadow_storage_err_qs;
2704             end
2705       
2706             default: begin
2707               reg_rdata_next = '1;
                   ==>

Branches:
-1-StatusTests
addr_hit[0] Covered T4,T5,T28
addr_hit[1] Covered T4,T5,T28
addr_hit[2] Covered T4,T5,T6
addr_hit[3] Covered T4,T5,T6
addr_hit[4] Covered T4,T5,T28
addr_hit[5] Covered T4,T5,T6
addr_hit[6] Covered T4,T5,T6
addr_hit[7] Covered T4,T5,T28
addr_hit[8] Covered T4,T5,T6
addr_hit[9] Covered T4,T5,T6
addr_hit[10] Covered T4,T5,T6
addr_hit[11] Covered T4,T5,T6
addr_hit[12] Covered T4,T5,T28
addr_hit[13] Covered T4,T5,T6
addr_hit[14] Covered T4,T5,T6
addr_hit[15] Covered T4,T5,T6
addr_hit[16] Covered T4,T5,T6
addr_hit[17] Covered T4,T5,T6
addr_hit[18] Covered T4,T5,T6
addr_hit[19] Covered T4,T5,T6
addr_hit[20] Covered T4,T5,T6
addr_hit[21] Covered T4,T5,T6
default Covered T4,T5,T6 



2717           if (!rst_ni) begin
               -1-  
2718             rst_done <= '0;
                 ==>
2719           end else begin
2720             rst_done <= 1'b1;
                 ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



2725           if (!rst_shadowed_ni) begin
               -1-  
2726             shadow_rst_done <= '0;
                 ==>
2727           end else begin
2728             shadow_rst_done <= 1'b1;
                 ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



2766           unique case (1'b1)
                      -1-  
2767             addr_hit[10]: begin
2768               reg_busy_sel = io_meas_ctrl_en_busy;
                   ==>
2769             end
2770             addr_hit[11]: begin
2771               reg_busy_sel = io_meas_ctrl_shadowed_busy;
                   ==>
2772             end
2773             addr_hit[12]: begin
2774               reg_busy_sel = io_div2_meas_ctrl_en_busy;
                   ==>
2775             end
2776             addr_hit[13]: begin
2777               reg_busy_sel = io_div2_meas_ctrl_shadowed_busy;
                   ==>
2778             end
2779             addr_hit[14]: begin
2780               reg_busy_sel = io_div4_meas_ctrl_en_busy;
                   ==>
2781             end
2782             addr_hit[15]: begin
2783               reg_busy_sel = io_div4_meas_ctrl_shadowed_busy;
                   ==>
2784             end
2785             addr_hit[16]: begin
2786               reg_busy_sel = main_meas_ctrl_en_busy;
                   ==>
2787             end
2788             addr_hit[17]: begin
2789               reg_busy_sel = main_meas_ctrl_shadowed_busy;
                   ==>
2790             end
2791             addr_hit[18]: begin
2792               reg_busy_sel = usb_meas_ctrl_en_busy;
                   ==>
2793             end
2794             addr_hit[19]: begin
2795               reg_busy_sel = usb_meas_ctrl_shadowed_busy;
                   ==>
2796             end
2797             default: begin
2798               reg_busy_sel  = '0;
                   ==>

Branches:
-1-StatusTests
addr_hit[10] Covered T4,T5,T6
addr_hit[11] Covered T4,T5,T6
addr_hit[12] Covered T4,T5,T28
addr_hit[13] Covered T4,T5,T6
addr_hit[14] Covered T4,T5,T6
addr_hit[15] Covered T4,T5,T6
addr_hit[16] Covered T4,T5,T6
addr_hit[17] Covered T4,T5,T6
addr_hit[18] Covered T4,T5,T6
addr_hit[19] Covered T4,T5,T6
default Covered T4,T5,T6

Assert Coverage for Module : clkmgr_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 38949284 337617 0 0
reAfterRv 38949284 337617 0 0
rePulse 38949284 114245 0 0
wePulse 38949284 223372 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 38949284 337617 0 0
T4 1319 31 0 0
T5 1695 81 0 0
T6 1044 39 0 0
T28 1332 4 0 0
T29 1111 0 0 0
T30 1397 49 0 0
T31 2924 49 0 0
T32 1677 41 0 0
T33 1440 42 0 0
T34 2557 61 0 0
T82 0 81 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 38949284 337617 0 0
T4 1319 31 0 0
T5 1695 81 0 0
T6 1044 39 0 0
T28 1332 4 0 0
T29 1111 0 0 0
T30 1397 49 0 0
T31 2924 49 0 0
T32 1677 41 0 0
T33 1440 42 0 0
T34 2557 61 0 0
T82 0 81 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 38949284 114245 0 0
T4 1319 10 0 0
T5 1695 42 0 0
T6 1044 0 0 0
T28 1332 1 0 0
T29 1111 0 0 0
T30 1397 28 0 0
T31 2924 16 0 0
T32 1677 24 0 0
T33 1440 24 0 0
T34 2557 20 0 0
T82 0 42 0 0
T123 0 9 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 38949284 223372 0 0
T4 1319 21 0 0
T5 1695 39 0 0
T6 1044 39 0 0
T28 1332 3 0 0
T29 1111 0 0 0
T30 1397 21 0 0
T31 2924 33 0 0
T32 1677 17 0 0
T33 1440 18 0 0
T34 2557 41 0 0
T82 0 39 0 0

Line Coverage for Instance : tb.dut.u_reg
Line No.TotalCoveredPercent
TOTAL244244100.00
ALWAYS8244100.00
CONT_ASSIGN9111100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
ALWAYS27744100.00
CONT_ASSIGN30711100.00
ALWAYS32033100.00
CONT_ASSIGN34911100.00
ALWAYS36344100.00
CONT_ASSIGN39311100.00
ALWAYS40633100.00
CONT_ASSIGN43511100.00
ALWAYS44944100.00
CONT_ASSIGN47911100.00
ALWAYS49233100.00
CONT_ASSIGN52111100.00
ALWAYS53544100.00
CONT_ASSIGN56511100.00
ALWAYS57833100.00
CONT_ASSIGN60711100.00
ALWAYS62144100.00
CONT_ASSIGN65111100.00
ALWAYS66433100.00
CONT_ASSIGN69311100.00
CONT_ASSIGN70011100.00
CONT_ASSIGN71511100.00
CONT_ASSIGN73111100.00
CONT_ASSIGN76511100.00
CONT_ASSIGN125311100.00
CONT_ASSIGN125611100.00
CONT_ASSIGN128711100.00
CONT_ASSIGN141011100.00
CONT_ASSIGN141311100.00
CONT_ASSIGN144511100.00
CONT_ASSIGN156811100.00
CONT_ASSIGN157111100.00
CONT_ASSIGN160311100.00
CONT_ASSIGN172611100.00
CONT_ASSIGN172911100.00
CONT_ASSIGN176111100.00
CONT_ASSIGN188411100.00
CONT_ASSIGN188711100.00
CONT_ASSIGN191811100.00
ALWAYS24242323100.00
CONT_ASSIGN244911100.00
ALWAYS245311100.00
CONT_ASSIGN247911100.00
CONT_ASSIGN248111100.00
CONT_ASSIGN248311100.00
CONT_ASSIGN248411100.00
CONT_ASSIGN248611100.00
CONT_ASSIGN248711100.00
CONT_ASSIGN248911100.00
CONT_ASSIGN249111100.00
CONT_ASSIGN249211100.00
CONT_ASSIGN249311100.00
CONT_ASSIGN249511100.00
CONT_ASSIGN249611100.00
CONT_ASSIGN249811100.00
CONT_ASSIGN249911100.00
CONT_ASSIGN250111100.00
CONT_ASSIGN250311100.00
CONT_ASSIGN250511100.00
CONT_ASSIGN250711100.00
CONT_ASSIGN250811100.00
CONT_ASSIGN251011100.00
CONT_ASSIGN251211100.00
CONT_ASSIGN251411100.00
CONT_ASSIGN251611100.00
CONT_ASSIGN251711100.00
CONT_ASSIGN251911100.00
CONT_ASSIGN252011100.00
CONT_ASSIGN252211100.00
CONT_ASSIGN252311100.00
CONT_ASSIGN252611100.00
CONT_ASSIGN252811100.00
CONT_ASSIGN252911100.00
CONT_ASSIGN253211100.00
CONT_ASSIGN253411100.00
CONT_ASSIGN253511100.00
CONT_ASSIGN253811100.00
CONT_ASSIGN254011100.00
CONT_ASSIGN254111100.00
CONT_ASSIGN254411100.00
CONT_ASSIGN254611100.00
CONT_ASSIGN254711100.00
CONT_ASSIGN255011100.00
CONT_ASSIGN255211100.00
CONT_ASSIGN255411100.00
CONT_ASSIGN255611100.00
CONT_ASSIGN255811100.00
CONT_ASSIGN256011100.00
CONT_ASSIGN256211100.00
CONT_ASSIGN256411100.00
CONT_ASSIGN256611100.00
CONT_ASSIGN256811100.00
CONT_ASSIGN257011100.00
CONT_ASSIGN257211100.00
ALWAYS25762323100.00
ALWAYS26034747100.00
ALWAYS271733100.00
ALWAYS272533100.00
CONT_ASSIGN273311100.00
CONT_ASSIGN273611100.00
CONT_ASSIGN274811100.00
CONT_ASSIGN276311100.00
ALWAYS27651212100.00
CONT_ASSIGN281011100.00
CONT_ASSIGN281111100.00

Click here to see the source line report.
Cond Coverage for Instance : tb.dut.u_reg
TotalCoveredPercent
Conditions289289100.00
Logical289289100.00
Non-Logical00
Event00

 LINE       72
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT36,T40,T90
11CoveredT4,T5,T6 

 LINE       84
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT78,T21,T81
10CoveredT141,T142,T143 

 LINE       91
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT78,T21,T81
010CoveredT141,T142,T143
100CoveredT78,T21,T81 

 LINE       133
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT4,T5,T6
001CoveredT141,T142,T143
010CoveredT36,T40,T90
100CoveredT36,T40,T90 

 LINE       765
 EXPRESSION (extclk_ctrl_we & extclk_ctrl_regwen_qs)
             -------1------   ----------2----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT2,T10,T27
11CoveredT4,T28,T31 

 LINE       1256
 EXPRESSION (io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen)
             ----------1----------   ------------2------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1287
 EXPRESSION (io_io_meas_ctrl_shadowed_we & io_io_meas_ctrl_shadowed_regwen)
             -------------1-------------   ---------------2---------------
-1--2-StatusTests
01CoveredT2,T10,T27
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1413
 EXPRESSION (io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1445
 EXPRESSION (io_div2_io_div2_meas_ctrl_shadowed_we & io_div2_io_div2_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT2,T10,T27
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1571
 EXPRESSION (io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1603
 EXPRESSION (io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen)
             ------------------1------------------   --------------------2--------------------
-1--2-StatusTests
01CoveredT2,T10,T27
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1729
 EXPRESSION (main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen)
             ------------1------------   --------------2--------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1761
 EXPRESSION (main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen)
             ---------------1---------------   -----------------2-----------------
-1--2-StatusTests
01CoveredT2,T10,T27
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1887
 EXPRESSION (usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen)
             -----------1-----------   -------------2-------------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       1918
 EXPRESSION (usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen)
             --------------1--------------   ----------------2----------------
-1--2-StatusTests
01CoveredT2,T10,T27
10CoveredT2,T10,T27
11CoveredT1,T2,T3 

 LINE       2425
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T32,T84 

 LINE       2426
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET)
            -------------------------------1------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T28 

 LINE       2427
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_CTRL_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       2428
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_EXTCLK_STATUS_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T32 

 LINE       2429
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_REGWEN_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T1,T2 

 LINE       2430
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_JITTER_ENABLE_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T32 

 LINE       2431
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_ENABLES_OFFSET)
            ---------------------------1---------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T82 

 LINE       2432
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_OFFSET)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T30,T33 

 LINE       2433
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_CLK_HINTS_STATUS_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T30 

 LINE       2434
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MEASURE_CTRL_REGWEN_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T133 

 LINE       2435
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_EN_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T32 

 LINE       2436
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET)
            --------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T133 

 LINE       2437
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T32,T133 

 LINE       2438
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T32 

 LINE       2439
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET)
            --------------------------------1-------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T1 

 LINE       2440
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET)
            -----------------------------------1----------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T32 

 LINE       2441
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET)
            ------------------------------1------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T133 

 LINE       2442
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1---------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T32 

 LINE       2443
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_EN_OFFSET)
            ------------------------------1-----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T1 

 LINE       2444
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET)
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T133 

 LINE       2445
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_RECOV_ERR_CODE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T32 

 LINE       2446
 EXPRESSION (reg_addr == clkmgr_reg_pkg::CLKMGR_FATAL_ERR_CODE_OFFSET)
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT5,T6,T32 

 LINE       2449
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT4,T5,T6 

 LINE       2449
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT4,T5,T6
10CoveredT4,T5,T28 

 LINE       2453
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T6
11CoveredT36,T40,T90 

 LINE       2453
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0111 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b0111 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b0011 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT4,T5,T6
22 (addr_hit[21] & ((|(4'...CoveredT6,T85,T1
21 (addr_hit[20] & ((|(4'...CoveredT5,T6,T32
20 (addr_hit[19] & ((|(4'...CoveredT5,T6,T133
19 (addr_hit[18] & ((|(4'...CoveredT5,T1,T2
18 (addr_hit[17] & ((|(4'...CoveredT5,T6,T32
17 (addr_hit[16] & ((|(4'...CoveredT5,T6,T133
16 (addr_hit[15] & ((|(4'...CoveredT5,T133,T1
15 (addr_hit[14] & ((|(4'...CoveredT5,T1,T23
14 (addr_hit[13] & ((|(4'...CoveredT5,T6,T32
13 (addr_hit[12] & ((|(4'...CoveredT32,T133,T1
12 (addr_hit[11] & ((|(4'...CoveredT5,T6,T133
11 (addr_hit[10] & ((|(4'...CoveredT5,T6,T32
10 (addr_hit[9] & ((|(4'b...CoveredT5,T1,T2
9 (addr_hit[8] & ((|(4'b...CoveredT5,T6,T30
8 (addr_hit[7] & ((|(4'b...CoveredT5,T85,T1
7 (addr_hit[6] & ((|(4'b...CoveredT6,T82,T133
6 (addr_hit[5] & ((|(4'b...CoveredT5,T6,T82
5 (addr_hit[4] & ((|(4'b...CoveredT5,T1,T2
4 (addr_hit[3] & ((|(4'b...CoveredT5,T6,T32
3 (addr_hit[2] & ((|(4'b...CoveredT4,T5,T28
2 (addr_hit[1] & ((|(4'b...CoveredT5,T133,T1
1 (addr_hit[0] & ((|(4'b...CoveredT5,T133,T2 

 LINE       2453
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T32,T84
11CoveredT5,T133,T2 

 LINE       2453
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT4,T5,T28
11CoveredT5,T133,T1 

 LINE       2453
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT5,T6,T30
10CoveredT4,T6,T28
11CoveredT4,T5,T28 

 LINE       2453
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T32
11CoveredT5,T6,T32 

 LINE       2453
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T27
11CoveredT5,T1,T2 

 LINE       2453
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T32,T82
11CoveredT5,T6,T82 

 LINE       2453
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T82
11CoveredT6,T82,T133 

 LINE       2453
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T30,T33
11CoveredT5,T85,T1 

 LINE       2453
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T30,T33
11CoveredT5,T6,T30 

 LINE       2453
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T133
11CoveredT5,T1,T2 

 LINE       2453
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T85
11CoveredT5,T6,T32 

 LINE       2453
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T3
11CoveredT5,T6,T133 

 LINE       2453
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T32,T133
11CoveredT32,T133,T1 

 LINE       2453
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT32,T1,T2
11CoveredT5,T6,T32 

 LINE       2453
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T1
11CoveredT5,T1,T23 

 LINE       2453
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT6,T32,T1
11CoveredT5,T133,T1 

 LINE       2453
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T1,T2
11CoveredT5,T6,T133 

 LINE       2453
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT32,T1,T2
11CoveredT5,T6,T32 

 LINE       2453
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T1
11CoveredT5,T1,T2 

 LINE       2453
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT85,T1,T2
11CoveredT5,T6,T133 

 LINE       2453
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT32,T1,T2
11CoveredT5,T6,T32 

 LINE       2453
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T32
11CoveredT6,T85,T1 

 LINE       2479
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T32,T84
110CoveredT36,T40,T90
111CoveredT84,T85,T86 

 LINE       2484
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT4,T5,T28
110CoveredT36,T40,T90
111CoveredT4,T28,T31 

 LINE       2487
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT4,T5,T6
110CoveredT36,T40,T90
111CoveredT4,T28,T31 

 LINE       2492
 EXPRESSION (addr_hit[3] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T28
101CoveredT5,T6,T32
110CoveredT144,T145
111CoveredT32,T123,T20 

 LINE       2493
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T1,T2
110CoveredT36,T40,T90
111CoveredT146,T127,T128 

 LINE       2496
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T32
110CoveredT36,T40,T90
111CoveredT5,T82,T83 

 LINE       2499
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T28
101CoveredT5,T6,T82
110CoveredT36,T40,T90
111CoveredT5,T6,T82 

 LINE       2508
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T30,T33
110CoveredT36,T40,T90
111CoveredT5,T30,T33 

 LINE       2517
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T133
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2520
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T32
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2522
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T28
101CoveredT5,T6,T79
110CoveredT144
111CoveredT2,T10,T27 

 LINE       2523
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T79
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2526
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T32,T133
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2528
 EXPRESSION (addr_hit[13] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T28
101CoveredT5,T6,T32
110CoveredT147,T144,T148
111CoveredT2,T10,T27 

 LINE       2529
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T32
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2532
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T1
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2534
 EXPRESSION (addr_hit[15] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T28
101CoveredT5,T6,T32
110CoveredT149,T150,T151
111CoveredT2,T10,T27 

 LINE       2535
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T32
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2538
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T133
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2540
 EXPRESSION (addr_hit[17] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T28
101CoveredT5,T6,T32
110CoveredT142,T145
111CoveredT2,T10,T27 

 LINE       2541
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T32
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2544
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T1
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2546
 EXPRESSION (addr_hit[19] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T28
101CoveredT5,T6,T133
110CoveredT152
111CoveredT2,T10,T27 

 LINE       2547
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T133
110CoveredT36,T40,T90
111CoveredT1,T2,T3 

 LINE       2550
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT5,T6,T32
110CoveredT36,T40,T90
111CoveredT1,T3,T51 

 LINE       2733
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------
-1--2-StatusTests
01CoveredT100,T102,T101
10CoveredT10,T27,T26
11CoveredT4,T5,T6 

 LINE       2763
 EXPRESSION (reg_busy_sel | shadow_busy)
             ------1-----   -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT5,T6,T32
10CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_reg
Line No.TotalCoveredPercent
Branches 43 43 100.00
TERNARY 2449 2 2 100.00
IF 82 3 3 100.00
CASE 2604 23 23 100.00
IF 2717 2 2 100.00
IF 2725 2 2 100.00
CASE 2766 11 11 100.00 



2449         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



82             if (!rst_ni) begin
               -1-  
83               err_q <= '0;
                 ==>
84             end else if (intg_err || reg_we_err) begin
                        -2-  
85               err_q <= 1'b1;
                 ==>
86             end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T78,T21,T81
0 0 Covered T4,T5,T6 



2604           unique case (1'b1)
                      -1-  
2605             addr_hit[0]: begin
2606               reg_rdata_next[0] = '0;
                   ==>
2607               reg_rdata_next[1] = '0;
2608             end
2609       
2610             addr_hit[1]: begin
2611               reg_rdata_next[0] = extclk_ctrl_regwen_qs;
                   ==>
2612             end
2613       
2614             addr_hit[2]: begin
2615               reg_rdata_next[3:0] = extclk_ctrl_sel_qs;
                   ==>
2616               reg_rdata_next[7:4] = extclk_ctrl_hi_speed_sel_qs;
2617             end
2618       
2619             addr_hit[3]: begin
2620               reg_rdata_next[3:0] = extclk_status_qs;
                   ==>
2621             end
2622       
2623             addr_hit[4]: begin
2624               reg_rdata_next[0] = jitter_regwen_qs;
                   ==>
2625             end
2626       
2627             addr_hit[5]: begin
2628               reg_rdata_next[3:0] = jitter_enable_qs;
                   ==>
2629             end
2630       
2631             addr_hit[6]: begin
2632               reg_rdata_next[0] = clk_enables_clk_io_div4_peri_en_qs;
                   ==>
2633               reg_rdata_next[1] = clk_enables_clk_io_div2_peri_en_qs;
2634               reg_rdata_next[2] = clk_enables_clk_io_peri_en_qs;
2635               reg_rdata_next[3] = clk_enables_clk_usb_peri_en_qs;
2636             end
2637       
2638             addr_hit[7]: begin
2639               reg_rdata_next[0] = clk_hints_clk_main_aes_hint_qs;
                   ==>
2640               reg_rdata_next[1] = clk_hints_clk_main_hmac_hint_qs;
2641               reg_rdata_next[2] = clk_hints_clk_main_kmac_hint_qs;
2642               reg_rdata_next[3] = clk_hints_clk_main_otbn_hint_qs;
2643             end
2644       
2645             addr_hit[8]: begin
2646               reg_rdata_next[0] = clk_hints_status_clk_main_aes_val_qs;
                   ==>
2647               reg_rdata_next[1] = clk_hints_status_clk_main_hmac_val_qs;
2648               reg_rdata_next[2] = clk_hints_status_clk_main_kmac_val_qs;
2649               reg_rdata_next[3] = clk_hints_status_clk_main_otbn_val_qs;
2650             end
2651       
2652             addr_hit[9]: begin
2653               reg_rdata_next[0] = measure_ctrl_regwen_qs;
                   ==>
2654             end
2655       
2656             addr_hit[10]: begin
2657               reg_rdata_next = DW'(io_meas_ctrl_en_qs);
                   ==>
2658             end
2659             addr_hit[11]: begin
2660               reg_rdata_next = DW'(io_meas_ctrl_shadowed_qs);
                   ==>
2661             end
2662             addr_hit[12]: begin
2663               reg_rdata_next = DW'(io_div2_meas_ctrl_en_qs);
                   ==>
2664             end
2665             addr_hit[13]: begin
2666               reg_rdata_next = DW'(io_div2_meas_ctrl_shadowed_qs);
                   ==>
2667             end
2668             addr_hit[14]: begin
2669               reg_rdata_next = DW'(io_div4_meas_ctrl_en_qs);
                   ==>
2670             end
2671             addr_hit[15]: begin
2672               reg_rdata_next = DW'(io_div4_meas_ctrl_shadowed_qs);
                   ==>
2673             end
2674             addr_hit[16]: begin
2675               reg_rdata_next = DW'(main_meas_ctrl_en_qs);
                   ==>
2676             end
2677             addr_hit[17]: begin
2678               reg_rdata_next = DW'(main_meas_ctrl_shadowed_qs);
                   ==>
2679             end
2680             addr_hit[18]: begin
2681               reg_rdata_next = DW'(usb_meas_ctrl_en_qs);
                   ==>
2682             end
2683             addr_hit[19]: begin
2684               reg_rdata_next = DW'(usb_meas_ctrl_shadowed_qs);
                   ==>
2685             end
2686             addr_hit[20]: begin
2687               reg_rdata_next[0] = recov_err_code_shadow_update_err_qs;
                   ==>
2688               reg_rdata_next[1] = recov_err_code_io_measure_err_qs;
2689               reg_rdata_next[2] = recov_err_code_io_div2_measure_err_qs;
2690               reg_rdata_next[3] = recov_err_code_io_div4_measure_err_qs;
2691               reg_rdata_next[4] = recov_err_code_main_measure_err_qs;
2692               reg_rdata_next[5] = recov_err_code_usb_measure_err_qs;
2693               reg_rdata_next[6] = recov_err_code_io_timeout_err_qs;
2694               reg_rdata_next[7] = recov_err_code_io_div2_timeout_err_qs;
2695               reg_rdata_next[8] = recov_err_code_io_div4_timeout_err_qs;
2696               reg_rdata_next[9] = recov_err_code_main_timeout_err_qs;
2697               reg_rdata_next[10] = recov_err_code_usb_timeout_err_qs;
2698             end
2699       
2700             addr_hit[21]: begin
2701               reg_rdata_next[0] = fatal_err_code_reg_intg_qs;
                   ==>
2702               reg_rdata_next[1] = fatal_err_code_idle_cnt_qs;
2703               reg_rdata_next[2] = fatal_err_code_shadow_storage_err_qs;
2704             end
2705       
2706             default: begin
2707               reg_rdata_next = '1;
                   ==>

Branches:
-1-StatusTests
addr_hit[0] Covered T4,T5,T28
addr_hit[1] Covered T4,T5,T28
addr_hit[2] Covered T4,T5,T6
addr_hit[3] Covered T4,T5,T6
addr_hit[4] Covered T4,T5,T28
addr_hit[5] Covered T4,T5,T6
addr_hit[6] Covered T4,T5,T6
addr_hit[7] Covered T4,T5,T28
addr_hit[8] Covered T4,T5,T6
addr_hit[9] Covered T4,T5,T6
addr_hit[10] Covered T4,T5,T6
addr_hit[11] Covered T4,T5,T6
addr_hit[12] Covered T4,T5,T28
addr_hit[13] Covered T4,T5,T6
addr_hit[14] Covered T4,T5,T6
addr_hit[15] Covered T4,T5,T6
addr_hit[16] Covered T4,T5,T6
addr_hit[17] Covered T4,T5,T6
addr_hit[18] Covered T4,T5,T6
addr_hit[19] Covered T4,T5,T6
addr_hit[20] Covered T4,T5,T6
addr_hit[21] Covered T4,T5,T6
default Covered T4,T5,T6 



2717           if (!rst_ni) begin
               -1-  
2718             rst_done <= '0;
                 ==>
2719           end else begin
2720             rst_done <= 1'b1;
                 ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



2725           if (!rst_shadowed_ni) begin
               -1-  
2726             shadow_rst_done <= '0;
                 ==>
2727           end else begin
2728             shadow_rst_done <= 1'b1;
                 ==>

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6 



2766           unique case (1'b1)
                      -1-  
2767             addr_hit[10]: begin
2768               reg_busy_sel = io_meas_ctrl_en_busy;
                   ==>
2769             end
2770             addr_hit[11]: begin
2771               reg_busy_sel = io_meas_ctrl_shadowed_busy;
                   ==>
2772             end
2773             addr_hit[12]: begin
2774               reg_busy_sel = io_div2_meas_ctrl_en_busy;
                   ==>
2775             end
2776             addr_hit[13]: begin
2777               reg_busy_sel = io_div2_meas_ctrl_shadowed_busy;
                   ==>
2778             end
2779             addr_hit[14]: begin
2780               reg_busy_sel = io_div4_meas_ctrl_en_busy;
                   ==>
2781             end
2782             addr_hit[15]: begin
2783               reg_busy_sel = io_div4_meas_ctrl_shadowed_busy;
                   ==>
2784             end
2785             addr_hit[16]: begin
2786               reg_busy_sel = main_meas_ctrl_en_busy;
                   ==>
2787             end
2788             addr_hit[17]: begin
2789               reg_busy_sel = main_meas_ctrl_shadowed_busy;
                   ==>
2790             end
2791             addr_hit[18]: begin
2792               reg_busy_sel = usb_meas_ctrl_en_busy;
                   ==>
2793             end
2794             addr_hit[19]: begin
2795               reg_busy_sel = usb_meas_ctrl_shadowed_busy;
                   ==>
2796             end
2797             default: begin
2798               reg_busy_sel  = '0;
                   ==>

Branches:
-1-StatusTests
addr_hit[10] Covered T4,T5,T6
addr_hit[11] Covered T4,T5,T6
addr_hit[12] Covered T4,T5,T28
addr_hit[13] Covered T4,T5,T6
addr_hit[14] Covered T4,T5,T6
addr_hit[15] Covered T4,T5,T6
addr_hit[16] Covered T4,T5,T6
addr_hit[17] Covered T4,T5,T6
addr_hit[18] Covered T4,T5,T6
addr_hit[19] Covered T4,T5,T6
default Covered T4,T5,T6

Assert Coverage for Instance : tb.dut.u_reg
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 38949284 337617 0 0
reAfterRv 38949284 337617 0 0
rePulse 38949284 114245 0 0
wePulse 38949284 223372 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 38949284 337617 0 0
T4 1319 31 0 0
T5 1695 81 0 0
T6 1044 39 0 0
T28 1332 4 0 0
T29 1111 0 0 0
T30 1397 49 0 0
T31 2924 49 0 0
T32 1677 41 0 0
T33 1440 42 0 0
T34 2557 61 0 0
T82 0 81 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 38949284 337617 0 0
T4 1319 31 0 0
T5 1695 81 0 0
T6 1044 39 0 0
T28 1332 4 0 0
T29 1111 0 0 0
T30 1397 49 0 0
T31 2924 49 0 0
T32 1677 41 0 0
T33 1440 42 0 0
T34 2557 61 0 0
T82 0 81 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 38949284 114245 0 0
T4 1319 10 0 0
T5 1695 42 0 0
T6 1044 0 0 0
T28 1332 1 0 0
T29 1111 0 0 0
T30 1397 28 0 0
T31 2924 16 0 0
T32 1677 24 0 0
T33 1440 24 0 0
T34 2557 20 0 0
T82 0 42 0 0
T123 0 9 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 38949284 223372 0 0
T4 1319 21 0 0
T5 1695 39 0 0
T6 1044 39 0 0
T28 1332 3 0 0
T29 1111 0 0 0
T30 1397 21 0 0
T31 2924 33 0 0
T32 1677 17 0 0
T33 1440 18 0 0
T34 2557 41 0 0
T82 0 39 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%