Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

22                      
23         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T78,T21,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	38016723	34891274	0	0
AllClkBypReqTrue_A	38016723	79251	0	0
IoClkBypReqFalse_A	38016723	34838139	0	2355
IoClkBypReqTrue_A	38016723	127728	0	0
LcClkBypAckFalse_A	38016723	34897524	0	0
LcClkBypAckTrue_A	38016723	73001	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	34891274	0	0
T4	1319	1094	0	0
T5	1695	1650	0	0
T6	1044	1021	0	0
T28	1332	1177	0	0
T29	1111	1068	0	0
T30	1397	1329	0	0
T31	2924	2731	0	0
T32	1677	1431	0	0
T33	1440	1398	0	0
T34	2557	2212	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	79251	0	0
T4	1319	177	0	0
T5	1695	0	0	0
T6	1044	0	0	0
T28	1332	0	0	0
T29	1111	0	0	0
T30	1397	0	0	0
T31	2924	66	0	0
T32	1677	136	0	0
T33	1440	0	0	0
T34	2557	247	0	0
T123	0	8	0	0
T134	0	36	0	0
T153	0	134	0	0
T154	0	271	0	0
T155	0	44	0	0
T156	0	104	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	34838139	0	2355
T4	1319	1011	0	3
T5	1695	1648	0	3
T6	1044	1019	0	3
T28	1332	1175	0	3
T29	1111	1066	0	3
T30	1397	1327	0	3
T31	2924	2308	0	3
T32	1677	1439	0	3
T33	1440	1396	0	3
T34	2557	2092	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	127728	0	0
T4	1319	258	0	0
T5	1695	0	0	0
T6	1044	0	0	0
T28	1332	0	0	0
T29	1111	0	0	0
T30	1397	0	0	0
T31	2924	487	0	0
T32	1677	126	0	0
T33	1440	0	0	0
T34	2557	365	0	0
T123	0	53	0	0
T134	0	202	0	0
T153	0	224	0	0
T154	0	448	0	0
T155	0	40	0	0
T156	0	121	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	34897524	0	0
T4	1319	1144	0	0
T5	1695	1650	0	0
T6	1044	1021	0	0
T28	1332	1177	0	0
T29	1111	1068	0	0
T30	1397	1329	0	0
T31	2924	2656	0	0
T32	1677	1493	0	0
T33	1440	1398	0	0
T34	2557	2237	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	73001	0	0
T4	1319	127	0	0
T5	1695	0	0	0
T6	1044	0	0	0
T28	1332	0	0	0
T29	1111	0	0	0
T30	1397	0	0	0
T31	2924	141	0	0
T32	1677	74	0	0
T33	1440	0	0	0
T34	2557	222	0	0
T93	0	71	0	0
T123	0	31	0	0
T134	0	64	0	0
T153	0	149	0	0
T154	0	370	0	0
T156	0	79	0	0