Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	364608688	9121	0	0
TransStop_A	364608688	4726	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364608688	9121	0	0
T5	28260	4	0	0
T6	32112	0	0	0
T19	0	20	0	0
T24	0	4	0	0
T28	5332	0	0	0
T29	16840	0	0	0
T30	19956	15	0	0
T31	11700	0	0	0
T32	13972	0	0	0
T33	25048	10	0	0
T34	10332	0	0	0
T82	7964	4	0	0
T83	0	4	0	0
T96	0	7	0	0
T157	0	38	0	0
T158	0	25	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364608688	4726	0	0
T5	28260	4	0	0
T6	32112	0	0	0
T19	0	14	0	0
T24	0	4	0	0
T25	0	1	0	0
T28	5332	0	0	0
T29	16840	0	0	0
T30	19956	7	0	0
T31	11700	0	0	0
T32	13972	0	0	0
T33	25048	8	0	0
T34	10332	0	0	0
T82	7964	4	0	0
T83	0	4	0	0
T96	0	5	0	0
T157	0	25	0	0
T158	0	14	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	91152172	2287	0	0
TransStop_A	91152172	1203	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91152172	2287	0	0
T5	7065	1	0	0
T6	8028	0	0	0
T19	0	5	0	0
T24	0	1	0	0
T28	1333	0	0	0
T29	4210	0	0	0
T30	4989	3	0	0
T31	2925	0	0	0
T32	3493	0	0	0
T33	6262	3	0	0
T34	2583	0	0	0
T82	1991	1	0	0
T83	0	1	0	0
T96	0	1	0	0
T157	0	11	0	0
T158	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91152172	1203	0	0
T5	7065	1	0	0
T6	8028	0	0	0
T19	0	4	0	0
T24	0	1	0	0
T28	1333	0	0	0
T29	4210	0	0	0
T30	4989	1	0	0
T31	2925	0	0	0
T32	3493	0	0	0
T33	6262	3	0	0
T34	2583	0	0	0
T82	1991	1	0	0
T83	0	1	0	0
T96	0	1	0	0
T157	0	7	0	0
T158	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	91152172	2316	0	0
TransStop_A	91152172	1200	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91152172	2316	0	0
T5	7065	1	0	0
T6	8028	0	0	0
T19	0	3	0	0
T24	0	1	0	0
T28	1333	0	0	0
T29	4210	0	0	0
T30	4989	4	0	0
T31	2925	0	0	0
T32	3493	0	0	0
T33	6262	4	0	0
T34	2583	0	0	0
T82	1991	1	0	0
T83	0	1	0	0
T96	0	3	0	0
T157	0	9	0	0
T158	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91152172	1200	0	0
T5	7065	1	0	0
T6	8028	0	0	0
T19	0	2	0	0
T24	0	1	0	0
T28	1333	0	0	0
T29	4210	0	0	0
T30	4989	1	0	0
T31	2925	0	0	0
T32	3493	0	0	0
T33	6262	3	0	0
T34	2583	0	0	0
T82	1991	1	0	0
T83	0	1	0	0
T96	0	2	0	0
T157	0	6	0	0
T158	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	91152172	2283	0	0
TransStop_A	91152172	1188	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91152172	2283	0	0
T5	7065	1	0	0
T6	8028	0	0	0
T19	0	5	0	0
T24	0	1	0	0
T28	1333	0	0	0
T29	4210	0	0	0
T30	4989	4	0	0
T31	2925	0	0	0
T32	3493	0	0	0
T33	6262	1	0	0
T34	2583	0	0	0
T82	1991	1	0	0
T83	0	1	0	0
T96	0	1	0	0
T157	0	9	0	0
T158	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91152172	1188	0	0
T5	7065	1	0	0
T6	8028	0	0	0
T19	0	3	0	0
T24	0	1	0	0
T25	0	1	0	0
T28	1333	0	0	0
T29	4210	0	0	0
T30	4989	2	0	0
T31	2925	0	0	0
T32	3493	0	0	0
T33	6262	1	0	0
T34	2583	0	0	0
T82	1991	1	0	0
T83	0	1	0	0
T157	0	6	0	0
T158	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	91152172	2235	0	0
TransStop_A	91152172	1135	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91152172	2235	0	0
T5	7065	1	0	0
T6	8028	0	0	0
T19	0	7	0	0
T24	0	1	0	0
T28	1333	0	0	0
T29	4210	0	0	0
T30	4989	4	0	0
T31	2925	0	0	0
T32	3493	0	0	0
T33	6262	2	0	0
T34	2583	0	0	0
T82	1991	1	0	0
T83	0	1	0	0
T96	0	2	0	0
T157	0	9	0	0
T158	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91152172	1135	0	0
T5	7065	1	0	0
T6	8028	0	0	0
T19	0	5	0	0
T24	0	1	0	0
T28	1333	0	0	0
T29	4210	0	0	0
T30	4989	3	0	0
T31	2925	0	0	0
T32	3493	0	0	0
T33	6262	1	0	0
T34	2583	0	0	0
T82	1991	1	0	0
T83	0	1	0	0
T96	0	2	0	0
T157	0	6	0	0
T158	0	3	0	0