Line Coverage for Module :
clkmgr_trans
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 9 | 9 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
| ALWAYS | 140 | 4 | 4 | 100.00 |
| ALWAYS | 158 | 3 | 3 | 100.00 |
44 logic local_en;
45 1/1 assign idle_valid = (idle_cnt == IdleCntWidth'(TransIdleCnt));
Tests: T4 T5 T6
46 1/1 assign local_en = sw_hint_synced | ~idle_valid;
Tests: T4 T5 T6
47
48 prim_flop_2sync #(
49 .Width(1)
50 ) u_hint_sync (
51 .clk_i(clk_i),
52 .rst_ni(rst_ni),
53 .d_i(sw_hint_i),
54 .q_o(sw_hint_synced)
55 );
56
57 // Idle sync: Idle signal comes from IP module. The reset of the Idle signal
58 // may differ from the reset here. Adding mubi sync to synchronize.
59 prim_mubi_pkg::mubi4_t [0:0] idle;
60 prim_mubi4_sync #(
61 .NumCopies ( 1 ),
62 .AsyncOn ( 1'b 1 ),
63 .StabilityCheck ( 1'b 1 )
64 ) u_idle_sync (
65 .clk_i,
66 .rst_ni,
67 .mubi_i (idle_i),
68 .mubi_o (idle)
69 );
70
71 // SEC_CM: IDLE.CTR.REDUN
72 logic cnt_err;
73 prim_count #(
74 .Width(IdleCntWidth)
75 ) u_idle_cnt (
76 .clk_i(clk_i),
77 .rst_ni(rst_ni),
78 // the default condition is to keep the clock enabled
79 .clr_i(mubi4_test_false_loose(idle[0])),
80 .set_i('0),
81 .set_cnt_i('0),
82 .incr_en_i(mubi4_test_true_strict(idle[0]) & ~idle_valid),
83 .decr_en_i(1'b0),
84 .step_i(IdleCntWidth'(1'b1)),
85 .commit_i(1'b1),
86 .cnt_o(idle_cnt),
87 .cnt_after_commit_o(),
88 .err_o(cnt_err)
89 );
90
91 // Declared as size 1 packed array to avoid FPV warning.
92 prim_mubi_pkg::mubi4_t [0:0] scanmode;
93 prim_mubi4_sync #(
94 .NumCopies(1),
95 .AsyncOn(0)
96 ) u_scanmode_sync (
97 .clk_i,
98 .rst_ni,
99 .mubi_i(scanmode_i),
100 .mubi_o(scanmode)
101 );
102
103 // Add a prim buf here to make sure the CG and the lc sender inputs
104 // are derived from the same physical signal.
105 logic combined_en_d, combined_en_q;
106 prim_buf u_prim_buf_en (
107 .in_i(local_en & en_i),
108 .out_o(combined_en_d)
109 );
110
111 // clk_gated_i is already controlled by en_i, so there is no need
112 // to use it in the below gating function
113 prim_clock_gating #(
114 .FpgaBufGlobal(FpgaBufGlobal)
115 ) u_cg (
116 .clk_i(clk_gated_i),
117 .en_i(local_en),
118 .test_en_i(mubi4_test_true_strict(scanmode[0])),
119 .clk_o(clk_o)
120 );
121
122 // clock gated indication for alert handler
123 prim_mubi4_sender #(
124 .ResetValue(MuBi4True)
125 ) u_prim_mubi4_sender (
126 .clk_i(clk_i),
127 .rst_ni(rst_ni),
128 .mubi_i(combined_en_d ? MuBi4False : MuBi4True),
129 .mubi_o(alert_cg_en_o)
130 );
131
132 // we hold the error because there is no guarantee on
133 // what the timing of cnt_err looks like, it may be a
134 // pulse or it may be level. If it's for former,
135 // prim_sync_reqack may miss it, if it's the latter,
136 // prim_pulse_sync may miss it. As a result, just
137 // latch forever and sync it over.
138 logic hold_err;
139 always_ff @(posedge clk_i or negedge rst_ni) begin
140 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
141 1/1 hold_err <= '0;
Tests: T4 T5 T6
142 1/1 end else if (cnt_err) begin
Tests: T4 T5 T6
143 1/1 hold_err <= 1'b1;
Tests: T78 T21 T81
144 end
MISSING_ELSE
145 end
146
147 // register facing domain
148 prim_flop_2sync #(
149 .Width(1)
150 ) u_err_sync (
151 .clk_i(clk_reg_i),
152 .rst_ni(rst_reg_ni),
153 .d_i(hold_err),
154 .q_o(reg_cnt_err_o)
155 );
156
157 always_ff @(posedge clk_i or negedge rst_ni) begin
158 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
159 1/1 combined_en_q <= '0;
Tests: T4 T5 T6
160 end else begin
161 1/1 combined_en_q <= combined_en_d;
Tests: T4 T5 T6
Cond Coverage for Module :
clkmgr_trans
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 45
EXPRESSION (idle_cnt == 4'(TransIdleCnt))
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 46
EXPRESSION (sw_hint_synced | ((~idle_valid)))
-------1------ -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T30,T33 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
LINE 106
EXPRESSION (local_en & en_i)
----1--- --2-
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T30,T33 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 125
EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
Branch Coverage for Module :
clkmgr_trans
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
125 |
2 |
2 |
100.00 |
| IF |
140 |
3 |
3 |
100.00 |
| IF |
158 |
2 |
2 |
100.00 |
125 ) u_prim_mubi4_sender (
126 .clk_i(clk_i),
127 .rst_ni(rst_ni),
128 .mubi_i(combined_en_d ? MuBi4False : MuBi4True),
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
140 if (!rst_ni) begin
-1-
141 hold_err <= '0;
==>
142 end else if (cnt_err) begin
-2-
143 hold_err <= 1'b1;
==>
144 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T78,T21,T81 |
| 0 |
0 |
Covered |
T4,T5,T6 |
158 if (!rst_ni) begin
-1-
159 combined_en_q <= '0;
==>
160 end else begin
161 combined_en_q <= combined_en_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 9 | 9 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
| ALWAYS | 140 | 4 | 4 | 100.00 |
| ALWAYS | 158 | 3 | 3 | 100.00 |
44 logic local_en;
45 1/1 assign idle_valid = (idle_cnt == IdleCntWidth'(TransIdleCnt));
Tests: T4 T5 T6
46 1/1 assign local_en = sw_hint_synced | ~idle_valid;
Tests: T4 T5 T6
47
48 prim_flop_2sync #(
49 .Width(1)
50 ) u_hint_sync (
51 .clk_i(clk_i),
52 .rst_ni(rst_ni),
53 .d_i(sw_hint_i),
54 .q_o(sw_hint_synced)
55 );
56
57 // Idle sync: Idle signal comes from IP module. The reset of the Idle signal
58 // may differ from the reset here. Adding mubi sync to synchronize.
59 prim_mubi_pkg::mubi4_t [0:0] idle;
60 prim_mubi4_sync #(
61 .NumCopies ( 1 ),
62 .AsyncOn ( 1'b 1 ),
63 .StabilityCheck ( 1'b 1 )
64 ) u_idle_sync (
65 .clk_i,
66 .rst_ni,
67 .mubi_i (idle_i),
68 .mubi_o (idle)
69 );
70
71 // SEC_CM: IDLE.CTR.REDUN
72 logic cnt_err;
73 prim_count #(
74 .Width(IdleCntWidth)
75 ) u_idle_cnt (
76 .clk_i(clk_i),
77 .rst_ni(rst_ni),
78 // the default condition is to keep the clock enabled
79 .clr_i(mubi4_test_false_loose(idle[0])),
80 .set_i('0),
81 .set_cnt_i('0),
82 .incr_en_i(mubi4_test_true_strict(idle[0]) & ~idle_valid),
83 .decr_en_i(1'b0),
84 .step_i(IdleCntWidth'(1'b1)),
85 .commit_i(1'b1),
86 .cnt_o(idle_cnt),
87 .cnt_after_commit_o(),
88 .err_o(cnt_err)
89 );
90
91 // Declared as size 1 packed array to avoid FPV warning.
92 prim_mubi_pkg::mubi4_t [0:0] scanmode;
93 prim_mubi4_sync #(
94 .NumCopies(1),
95 .AsyncOn(0)
96 ) u_scanmode_sync (
97 .clk_i,
98 .rst_ni,
99 .mubi_i(scanmode_i),
100 .mubi_o(scanmode)
101 );
102
103 // Add a prim buf here to make sure the CG and the lc sender inputs
104 // are derived from the same physical signal.
105 logic combined_en_d, combined_en_q;
106 prim_buf u_prim_buf_en (
107 .in_i(local_en & en_i),
108 .out_o(combined_en_d)
109 );
110
111 // clk_gated_i is already controlled by en_i, so there is no need
112 // to use it in the below gating function
113 prim_clock_gating #(
114 .FpgaBufGlobal(FpgaBufGlobal)
115 ) u_cg (
116 .clk_i(clk_gated_i),
117 .en_i(local_en),
118 .test_en_i(mubi4_test_true_strict(scanmode[0])),
119 .clk_o(clk_o)
120 );
121
122 // clock gated indication for alert handler
123 prim_mubi4_sender #(
124 .ResetValue(MuBi4True)
125 ) u_prim_mubi4_sender (
126 .clk_i(clk_i),
127 .rst_ni(rst_ni),
128 .mubi_i(combined_en_d ? MuBi4False : MuBi4True),
129 .mubi_o(alert_cg_en_o)
130 );
131
132 // we hold the error because there is no guarantee on
133 // what the timing of cnt_err looks like, it may be a
134 // pulse or it may be level. If it's for former,
135 // prim_sync_reqack may miss it, if it's the latter,
136 // prim_pulse_sync may miss it. As a result, just
137 // latch forever and sync it over.
138 logic hold_err;
139 always_ff @(posedge clk_i or negedge rst_ni) begin
140 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
141 1/1 hold_err <= '0;
Tests: T4 T5 T6
142 1/1 end else if (cnt_err) begin
Tests: T4 T5 T6
143 1/1 hold_err <= 1'b1;
Tests: T78 T21 T81
144 end
MISSING_ELSE
145 end
146
147 // register facing domain
148 prim_flop_2sync #(
149 .Width(1)
150 ) u_err_sync (
151 .clk_i(clk_reg_i),
152 .rst_ni(rst_reg_ni),
153 .d_i(hold_err),
154 .q_o(reg_cnt_err_o)
155 );
156
157 always_ff @(posedge clk_i or negedge rst_ni) begin
158 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
159 1/1 combined_en_q <= '0;
Tests: T4 T5 T6
160 end else begin
161 1/1 combined_en_q <= combined_en_d;
Tests: T4 T5 T6
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 45
EXPRESSION (idle_cnt == 4'(TransIdleCnt))
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 46
EXPRESSION (sw_hint_synced | ((~idle_valid)))
-------1------ -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T30,T33 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
LINE 106
EXPRESSION (local_en & en_i)
----1--- --2-
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T30,T33 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 125
EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
125 |
2 |
2 |
100.00 |
| IF |
140 |
3 |
3 |
100.00 |
| IF |
158 |
2 |
2 |
100.00 |
125 ) u_prim_mubi4_sender (
126 .clk_i(clk_i),
127 .rst_ni(rst_ni),
128 .mubi_i(combined_en_d ? MuBi4False : MuBi4True),
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
140 if (!rst_ni) begin
-1-
141 hold_err <= '0;
==>
142 end else if (cnt_err) begin
-2-
143 hold_err <= 1'b1;
==>
144 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T78,T21,T81 |
| 0 |
0 |
Covered |
T4,T5,T6 |
158 if (!rst_ni) begin
-1-
159 combined_en_q <= '0;
==>
160 end else begin
161 combined_en_q <= combined_en_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 9 | 9 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
| ALWAYS | 140 | 4 | 4 | 100.00 |
| ALWAYS | 158 | 3 | 3 | 100.00 |
44 logic local_en;
45 1/1 assign idle_valid = (idle_cnt == IdleCntWidth'(TransIdleCnt));
Tests: T4 T5 T6
46 1/1 assign local_en = sw_hint_synced | ~idle_valid;
Tests: T4 T5 T6
47
48 prim_flop_2sync #(
49 .Width(1)
50 ) u_hint_sync (
51 .clk_i(clk_i),
52 .rst_ni(rst_ni),
53 .d_i(sw_hint_i),
54 .q_o(sw_hint_synced)
55 );
56
57 // Idle sync: Idle signal comes from IP module. The reset of the Idle signal
58 // may differ from the reset here. Adding mubi sync to synchronize.
59 prim_mubi_pkg::mubi4_t [0:0] idle;
60 prim_mubi4_sync #(
61 .NumCopies ( 1 ),
62 .AsyncOn ( 1'b 1 ),
63 .StabilityCheck ( 1'b 1 )
64 ) u_idle_sync (
65 .clk_i,
66 .rst_ni,
67 .mubi_i (idle_i),
68 .mubi_o (idle)
69 );
70
71 // SEC_CM: IDLE.CTR.REDUN
72 logic cnt_err;
73 prim_count #(
74 .Width(IdleCntWidth)
75 ) u_idle_cnt (
76 .clk_i(clk_i),
77 .rst_ni(rst_ni),
78 // the default condition is to keep the clock enabled
79 .clr_i(mubi4_test_false_loose(idle[0])),
80 .set_i('0),
81 .set_cnt_i('0),
82 .incr_en_i(mubi4_test_true_strict(idle[0]) & ~idle_valid),
83 .decr_en_i(1'b0),
84 .step_i(IdleCntWidth'(1'b1)),
85 .commit_i(1'b1),
86 .cnt_o(idle_cnt),
87 .cnt_after_commit_o(),
88 .err_o(cnt_err)
89 );
90
91 // Declared as size 1 packed array to avoid FPV warning.
92 prim_mubi_pkg::mubi4_t [0:0] scanmode;
93 prim_mubi4_sync #(
94 .NumCopies(1),
95 .AsyncOn(0)
96 ) u_scanmode_sync (
97 .clk_i,
98 .rst_ni,
99 .mubi_i(scanmode_i),
100 .mubi_o(scanmode)
101 );
102
103 // Add a prim buf here to make sure the CG and the lc sender inputs
104 // are derived from the same physical signal.
105 logic combined_en_d, combined_en_q;
106 prim_buf u_prim_buf_en (
107 .in_i(local_en & en_i),
108 .out_o(combined_en_d)
109 );
110
111 // clk_gated_i is already controlled by en_i, so there is no need
112 // to use it in the below gating function
113 prim_clock_gating #(
114 .FpgaBufGlobal(FpgaBufGlobal)
115 ) u_cg (
116 .clk_i(clk_gated_i),
117 .en_i(local_en),
118 .test_en_i(mubi4_test_true_strict(scanmode[0])),
119 .clk_o(clk_o)
120 );
121
122 // clock gated indication for alert handler
123 prim_mubi4_sender #(
124 .ResetValue(MuBi4True)
125 ) u_prim_mubi4_sender (
126 .clk_i(clk_i),
127 .rst_ni(rst_ni),
128 .mubi_i(combined_en_d ? MuBi4False : MuBi4True),
129 .mubi_o(alert_cg_en_o)
130 );
131
132 // we hold the error because there is no guarantee on
133 // what the timing of cnt_err looks like, it may be a
134 // pulse or it may be level. If it's for former,
135 // prim_sync_reqack may miss it, if it's the latter,
136 // prim_pulse_sync may miss it. As a result, just
137 // latch forever and sync it over.
138 logic hold_err;
139 always_ff @(posedge clk_i or negedge rst_ni) begin
140 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
141 1/1 hold_err <= '0;
Tests: T4 T5 T6
142 1/1 end else if (cnt_err) begin
Tests: T4 T5 T6
143 1/1 hold_err <= 1'b1;
Tests: T78 T21 T81
144 end
MISSING_ELSE
145 end
146
147 // register facing domain
148 prim_flop_2sync #(
149 .Width(1)
150 ) u_err_sync (
151 .clk_i(clk_reg_i),
152 .rst_ni(rst_reg_ni),
153 .d_i(hold_err),
154 .q_o(reg_cnt_err_o)
155 );
156
157 always_ff @(posedge clk_i or negedge rst_ni) begin
158 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
159 1/1 combined_en_q <= '0;
Tests: T4 T5 T6
160 end else begin
161 1/1 combined_en_q <= combined_en_d;
Tests: T4 T5 T6
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 45
EXPRESSION (idle_cnt == 4'(TransIdleCnt))
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 46
EXPRESSION (sw_hint_synced | ((~idle_valid)))
-------1------ -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T30,T33 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
LINE 106
EXPRESSION (local_en & en_i)
----1--- --2-
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T30,T33 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 125
EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
125 |
2 |
2 |
100.00 |
| IF |
140 |
3 |
3 |
100.00 |
| IF |
158 |
2 |
2 |
100.00 |
125 ) u_prim_mubi4_sender (
126 .clk_i(clk_i),
127 .rst_ni(rst_ni),
128 .mubi_i(combined_en_d ? MuBi4False : MuBi4True),
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
140 if (!rst_ni) begin
-1-
141 hold_err <= '0;
==>
142 end else if (cnt_err) begin
-2-
143 hold_err <= 1'b1;
==>
144 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T78,T21,T81 |
| 0 |
0 |
Covered |
T4,T5,T6 |
158 if (!rst_ni) begin
-1-
159 combined_en_q <= '0;
==>
160 end else begin
161 combined_en_q <= combined_en_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 9 | 9 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
| ALWAYS | 140 | 4 | 4 | 100.00 |
| ALWAYS | 158 | 3 | 3 | 100.00 |
44 logic local_en;
45 1/1 assign idle_valid = (idle_cnt == IdleCntWidth'(TransIdleCnt));
Tests: T4 T5 T6
46 1/1 assign local_en = sw_hint_synced | ~idle_valid;
Tests: T4 T5 T6
47
48 prim_flop_2sync #(
49 .Width(1)
50 ) u_hint_sync (
51 .clk_i(clk_i),
52 .rst_ni(rst_ni),
53 .d_i(sw_hint_i),
54 .q_o(sw_hint_synced)
55 );
56
57 // Idle sync: Idle signal comes from IP module. The reset of the Idle signal
58 // may differ from the reset here. Adding mubi sync to synchronize.
59 prim_mubi_pkg::mubi4_t [0:0] idle;
60 prim_mubi4_sync #(
61 .NumCopies ( 1 ),
62 .AsyncOn ( 1'b 1 ),
63 .StabilityCheck ( 1'b 1 )
64 ) u_idle_sync (
65 .clk_i,
66 .rst_ni,
67 .mubi_i (idle_i),
68 .mubi_o (idle)
69 );
70
71 // SEC_CM: IDLE.CTR.REDUN
72 logic cnt_err;
73 prim_count #(
74 .Width(IdleCntWidth)
75 ) u_idle_cnt (
76 .clk_i(clk_i),
77 .rst_ni(rst_ni),
78 // the default condition is to keep the clock enabled
79 .clr_i(mubi4_test_false_loose(idle[0])),
80 .set_i('0),
81 .set_cnt_i('0),
82 .incr_en_i(mubi4_test_true_strict(idle[0]) & ~idle_valid),
83 .decr_en_i(1'b0),
84 .step_i(IdleCntWidth'(1'b1)),
85 .commit_i(1'b1),
86 .cnt_o(idle_cnt),
87 .cnt_after_commit_o(),
88 .err_o(cnt_err)
89 );
90
91 // Declared as size 1 packed array to avoid FPV warning.
92 prim_mubi_pkg::mubi4_t [0:0] scanmode;
93 prim_mubi4_sync #(
94 .NumCopies(1),
95 .AsyncOn(0)
96 ) u_scanmode_sync (
97 .clk_i,
98 .rst_ni,
99 .mubi_i(scanmode_i),
100 .mubi_o(scanmode)
101 );
102
103 // Add a prim buf here to make sure the CG and the lc sender inputs
104 // are derived from the same physical signal.
105 logic combined_en_d, combined_en_q;
106 prim_buf u_prim_buf_en (
107 .in_i(local_en & en_i),
108 .out_o(combined_en_d)
109 );
110
111 // clk_gated_i is already controlled by en_i, so there is no need
112 // to use it in the below gating function
113 prim_clock_gating #(
114 .FpgaBufGlobal(FpgaBufGlobal)
115 ) u_cg (
116 .clk_i(clk_gated_i),
117 .en_i(local_en),
118 .test_en_i(mubi4_test_true_strict(scanmode[0])),
119 .clk_o(clk_o)
120 );
121
122 // clock gated indication for alert handler
123 prim_mubi4_sender #(
124 .ResetValue(MuBi4True)
125 ) u_prim_mubi4_sender (
126 .clk_i(clk_i),
127 .rst_ni(rst_ni),
128 .mubi_i(combined_en_d ? MuBi4False : MuBi4True),
129 .mubi_o(alert_cg_en_o)
130 );
131
132 // we hold the error because there is no guarantee on
133 // what the timing of cnt_err looks like, it may be a
134 // pulse or it may be level. If it's for former,
135 // prim_sync_reqack may miss it, if it's the latter,
136 // prim_pulse_sync may miss it. As a result, just
137 // latch forever and sync it over.
138 logic hold_err;
139 always_ff @(posedge clk_i or negedge rst_ni) begin
140 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
141 1/1 hold_err <= '0;
Tests: T4 T5 T6
142 1/1 end else if (cnt_err) begin
Tests: T4 T5 T6
143 1/1 hold_err <= 1'b1;
Tests: T78 T21 T81
144 end
MISSING_ELSE
145 end
146
147 // register facing domain
148 prim_flop_2sync #(
149 .Width(1)
150 ) u_err_sync (
151 .clk_i(clk_reg_i),
152 .rst_ni(rst_reg_ni),
153 .d_i(hold_err),
154 .q_o(reg_cnt_err_o)
155 );
156
157 always_ff @(posedge clk_i or negedge rst_ni) begin
158 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
159 1/1 combined_en_q <= '0;
Tests: T4 T5 T6
160 end else begin
161 1/1 combined_en_q <= combined_en_d;
Tests: T4 T5 T6
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 45
EXPRESSION (idle_cnt == 4'(TransIdleCnt))
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 46
EXPRESSION (sw_hint_synced | ((~idle_valid)))
-------1------ -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T30,T33 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
LINE 106
EXPRESSION (local_en & en_i)
----1--- --2-
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T30,T33 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 125
EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
125 |
2 |
2 |
100.00 |
| IF |
140 |
3 |
3 |
100.00 |
| IF |
158 |
2 |
2 |
100.00 |
125 ) u_prim_mubi4_sender (
126 .clk_i(clk_i),
127 .rst_ni(rst_ni),
128 .mubi_i(combined_en_d ? MuBi4False : MuBi4True),
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
140 if (!rst_ni) begin
-1-
141 hold_err <= '0;
==>
142 end else if (cnt_err) begin
-2-
143 hold_err <= 1'b1;
==>
144 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T78,T21,T81 |
| 0 |
0 |
Covered |
T4,T5,T6 |
158 if (!rst_ni) begin
-1-
159 combined_en_q <= '0;
==>
160 end else begin
161 combined_en_q <= combined_en_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 9 | 9 | 100.00 |
| CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
| ALWAYS | 140 | 4 | 4 | 100.00 |
| ALWAYS | 158 | 3 | 3 | 100.00 |
44 logic local_en;
45 1/1 assign idle_valid = (idle_cnt == IdleCntWidth'(TransIdleCnt));
Tests: T4 T5 T6
46 1/1 assign local_en = sw_hint_synced | ~idle_valid;
Tests: T4 T5 T6
47
48 prim_flop_2sync #(
49 .Width(1)
50 ) u_hint_sync (
51 .clk_i(clk_i),
52 .rst_ni(rst_ni),
53 .d_i(sw_hint_i),
54 .q_o(sw_hint_synced)
55 );
56
57 // Idle sync: Idle signal comes from IP module. The reset of the Idle signal
58 // may differ from the reset here. Adding mubi sync to synchronize.
59 prim_mubi_pkg::mubi4_t [0:0] idle;
60 prim_mubi4_sync #(
61 .NumCopies ( 1 ),
62 .AsyncOn ( 1'b 1 ),
63 .StabilityCheck ( 1'b 1 )
64 ) u_idle_sync (
65 .clk_i,
66 .rst_ni,
67 .mubi_i (idle_i),
68 .mubi_o (idle)
69 );
70
71 // SEC_CM: IDLE.CTR.REDUN
72 logic cnt_err;
73 prim_count #(
74 .Width(IdleCntWidth)
75 ) u_idle_cnt (
76 .clk_i(clk_i),
77 .rst_ni(rst_ni),
78 // the default condition is to keep the clock enabled
79 .clr_i(mubi4_test_false_loose(idle[0])),
80 .set_i('0),
81 .set_cnt_i('0),
82 .incr_en_i(mubi4_test_true_strict(idle[0]) & ~idle_valid),
83 .decr_en_i(1'b0),
84 .step_i(IdleCntWidth'(1'b1)),
85 .commit_i(1'b1),
86 .cnt_o(idle_cnt),
87 .cnt_after_commit_o(),
88 .err_o(cnt_err)
89 );
90
91 // Declared as size 1 packed array to avoid FPV warning.
92 prim_mubi_pkg::mubi4_t [0:0] scanmode;
93 prim_mubi4_sync #(
94 .NumCopies(1),
95 .AsyncOn(0)
96 ) u_scanmode_sync (
97 .clk_i,
98 .rst_ni,
99 .mubi_i(scanmode_i),
100 .mubi_o(scanmode)
101 );
102
103 // Add a prim buf here to make sure the CG and the lc sender inputs
104 // are derived from the same physical signal.
105 logic combined_en_d, combined_en_q;
106 prim_buf u_prim_buf_en (
107 .in_i(local_en & en_i),
108 .out_o(combined_en_d)
109 );
110
111 // clk_gated_i is already controlled by en_i, so there is no need
112 // to use it in the below gating function
113 prim_clock_gating #(
114 .FpgaBufGlobal(FpgaBufGlobal)
115 ) u_cg (
116 .clk_i(clk_gated_i),
117 .en_i(local_en),
118 .test_en_i(mubi4_test_true_strict(scanmode[0])),
119 .clk_o(clk_o)
120 );
121
122 // clock gated indication for alert handler
123 prim_mubi4_sender #(
124 .ResetValue(MuBi4True)
125 ) u_prim_mubi4_sender (
126 .clk_i(clk_i),
127 .rst_ni(rst_ni),
128 .mubi_i(combined_en_d ? MuBi4False : MuBi4True),
129 .mubi_o(alert_cg_en_o)
130 );
131
132 // we hold the error because there is no guarantee on
133 // what the timing of cnt_err looks like, it may be a
134 // pulse or it may be level. If it's for former,
135 // prim_sync_reqack may miss it, if it's the latter,
136 // prim_pulse_sync may miss it. As a result, just
137 // latch forever and sync it over.
138 logic hold_err;
139 always_ff @(posedge clk_i or negedge rst_ni) begin
140 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
141 1/1 hold_err <= '0;
Tests: T4 T5 T6
142 1/1 end else if (cnt_err) begin
Tests: T4 T5 T6
143 1/1 hold_err <= 1'b1;
Tests: T78 T21 T81
144 end
MISSING_ELSE
145 end
146
147 // register facing domain
148 prim_flop_2sync #(
149 .Width(1)
150 ) u_err_sync (
151 .clk_i(clk_reg_i),
152 .rst_ni(rst_reg_ni),
153 .d_i(hold_err),
154 .q_o(reg_cnt_err_o)
155 );
156
157 always_ff @(posedge clk_i or negedge rst_ni) begin
158 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
159 1/1 combined_en_q <= '0;
Tests: T4 T5 T6
160 end else begin
161 1/1 combined_en_q <= combined_en_d;
Tests: T4 T5 T6
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans
| Total | Covered | Percent |
|---|
| Conditions | 10 | 10 | 100.00 |
| Logical | 10 | 10 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 45
EXPRESSION (idle_cnt == 4'(TransIdleCnt))
---------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 46
EXPRESSION (sw_hint_synced | ((~idle_valid)))
-------1------ -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T30,T33 |
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
LINE 106
EXPRESSION (local_en & en_i)
----1--- --2-
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T30,T33 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 125
EXPRESSION (combined_en_d ? MuBi4False : MuBi4True)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans
| Line No. | Total | Covered | Percent |
| Branches |
|
7 |
7 |
100.00 |
| TERNARY |
125 |
2 |
2 |
100.00 |
| IF |
140 |
3 |
3 |
100.00 |
| IF |
158 |
2 |
2 |
100.00 |
125 ) u_prim_mubi4_sender (
126 .clk_i(clk_i),
127 .rst_ni(rst_ni),
128 .mubi_i(combined_en_d ? MuBi4False : MuBi4True),
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
140 if (!rst_ni) begin
-1-
141 hold_err <= '0;
==>
142 end else if (cnt_err) begin
-2-
143 hold_err <= 1'b1;
==>
144 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T4,T5,T6 |
| 0 |
1 |
Covered |
T78,T21,T81 |
| 0 |
0 |
Covered |
T4,T5,T6 |
158 if (!rst_ni) begin
-1-
159 combined_en_q <= '0;
==>
160 end else begin
161 combined_en_q <= combined_en_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |