Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	38949284	476779	0	0
clk_enables_rd_A	38949284	9292	0	0
clk_hints_rd_A	38949284	8873	0	0
extclk_ctrl_rd_A	38949284	11721	0	0
extclk_ctrl_regwen_rd_A	38949284	6773	0	0
jitter_enable_rd_A	38949284	18028	0	0
jitter_regwen_rd_A	38949284	6908	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38949284	476779	0	0
T36	83618	1971	0	0
T37	49873	0	0	0
T38	30612	0	0	0
T40	0	5493	0	0
T90	0	5556	0	0
T109	0	4615	0	0
T110	0	8164	0	0
T111	0	3940	0	0
T112	0	7961	0	0
T113	0	3461	0	0
T114	0	8898	0	0
T115	0	8248	0	0
T116	1937	0	0	0
T117	80796	0	0	0
T118	1195	0	0	0
T119	813	0	0	0
T120	71402	0	0	0
T121	2778	0	0	0
T122	92577	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38949284	9292	0	0
T5	1695	1	0	0
T6	1044	0	0	0
T24	0	2	0	0
T28	1332	0	0	0
T29	1111	0	0	0
T30	1397	0	0	0
T31	2924	0	0	0
T32	1677	0	0	0
T33	1440	0	0	0
T34	2557	0	0	0
T36	0	84	0	0
T76	0	1	0	0
T82	1931	0	0	0
T111	0	202	0	0
T122	0	5	0	0
T175	0	6	0	0
T176	0	2	0	0
T177	0	17	0	0
T178	0	5	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38949284	8873	0	0
T5	1695	1	0	0
T6	1044	0	0	0
T24	0	1	0	0
T28	1332	0	0	0
T29	1111	0	0	0
T30	1397	0	0	0
T31	2924	0	0	0
T32	1677	0	0	0
T33	1440	0	0	0
T34	2557	0	0	0
T36	0	85	0	0
T76	0	4	0	0
T82	1931	0	0	0
T116	0	3	0	0
T122	0	2	0	0
T175	0	4	0	0
T176	0	3	0	0
T177	0	11	0	0
T178	0	3	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38949284	11721	0	0
T18	0	46	0	0
T26	0	39	0	0
T31	2924	59	0	0
T32	1677	0	0	0
T33	1440	0	0	0
T34	2557	0	0	0
T79	1276	0	0	0
T80	1499	0	0	0
T82	1931	0	0	0
T84	1990	0	0	0
T97	0	30	0	0
T123	1482	0	0	0
T133	976	0	0	0
T134	0	19	0	0
T179	0	15	0	0
T180	0	55	0	0
T181	0	64	0	0
T182	0	60	0	0
T183	0	28	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38949284	6773	0	0
T8	43492	0	0	0
T26	66184	19	0	0
T36	0	75	0	0
T65	1603	0	0	0
T66	1344	0	0	0
T67	2317	0	0	0
T68	11808	0	0	0
T69	1800	0	0	0
T70	1301	0	0	0
T111	0	193	0	0
T113	0	149	0	0
T126	0	32	0	0
T175	2534	0	0	0
T184	0	37	0	0
T185	0	47	0	0
T186	0	42	0	0
T187	0	113	0	0
T188	0	32	0	0
T189	1497	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38949284	18028	0	0
T5	1695	57	0	0
T6	1044	0	0	0
T24	0	110	0	0
T28	1332	0	0	0
T29	1111	0	0	0
T30	1397	0	0	0
T31	2924	0	0	0
T32	1677	0	0	0
T33	1440	0	0	0
T34	2557	0	0	0
T36	0	208	0	0
T76	0	123	0	0
T82	1931	0	0	0
T116	0	118	0	0
T122	0	224	0	0
T175	0	155	0	0
T176	0	122	0	0
T177	0	464	0	0
T178	0	111	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38949284	6908	0	0
T36	83618	87	0	0
T37	49873	0	0	0
T38	30612	0	0	0
T111	0	174	0	0
T113	0	195	0	0
T116	1937	0	0	0
T117	80796	0	0	0
T118	1195	0	0	0
T119	813	0	0	0
T120	71402	0	0	0
T121	2778	0	0	0
T122	92577	0	0	0
T187	0	212	0	0
T190	0	237	0	0
T191	0	123	0	0
T192	0	82	0	0
T193	0	104	0	0
T194	0	342	0	0
T195	0	163	0	0