Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	114050169	388	0	0
StatusRise_A	114050169	388	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114050169	388	0	0
T29	3333	8	0	0
T30	4191	0	0	0
T31	8772	0	0	0
T32	5031	0	0	0
T33	4320	0	0	0
T34	7671	0	0	0
T53	0	4	0	0
T79	3828	5	0	0
T80	4497	9	0	0
T82	5793	0	0	0
T84	5970	0	0	0
T94	0	15	0	0
T98	0	4	0	0
T196	0	3	0	0
T197	0	7	0	0
T198	0	9	0	0
T199	0	6	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114050169	388	0	0
T29	3333	8	0	0
T30	4191	0	0	0
T31	8772	0	0	0
T32	5031	0	0	0
T33	4320	0	0	0
T34	7671	0	0	0
T53	0	4	0	0
T79	3828	5	0	0
T80	4497	9	0	0
T82	5793	0	0	0
T84	5970	0	0	0
T94	0	15	0	0
T98	0	4	0	0
T196	0	3	0	0
T197	0	7	0	0
T198	0	9	0	0
T199	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38016723	134	0	0
StatusRise_A	38016723	134	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	134	0	0
T29	1111	2	0	0
T30	1397	0	0	0
T31	2924	0	0	0
T32	1677	0	0	0
T33	1440	0	0	0
T34	2557	0	0	0
T53	0	1	0	0
T79	1276	2	0	0
T80	1499	3	0	0
T82	1931	0	0	0
T84	1990	0	0	0
T94	0	5	0	0
T98	0	1	0	0
T196	0	1	0	0
T197	0	3	0	0
T198	0	4	0	0
T199	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	134	0	0
T29	1111	2	0	0
T30	1397	0	0	0
T31	2924	0	0	0
T32	1677	0	0	0
T33	1440	0	0	0
T34	2557	0	0	0
T53	0	1	0	0
T79	1276	2	0	0
T80	1499	3	0	0
T82	1931	0	0	0
T84	1990	0	0	0
T94	0	5	0	0
T98	0	1	0	0
T196	0	1	0	0
T197	0	3	0	0
T198	0	4	0	0
T199	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38016723	127	0	0
StatusRise_A	38016723	127	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	127	0	0
T29	1111	3	0	0
T30	1397	0	0	0
T31	2924	0	0	0
T32	1677	0	0	0
T33	1440	0	0	0
T34	2557	0	0	0
T53	0	1	0	0
T79	1276	2	0	0
T80	1499	3	0	0
T82	1931	0	0	0
T84	1990	0	0	0
T94	0	5	0	0
T98	0	2	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	3	0	0
T199	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	127	0	0
T29	1111	3	0	0
T30	1397	0	0	0
T31	2924	0	0	0
T32	1677	0	0	0
T33	1440	0	0	0
T34	2557	0	0	0
T53	0	1	0	0
T79	1276	2	0	0
T80	1499	3	0	0
T82	1931	0	0	0
T84	1990	0	0	0
T94	0	5	0	0
T98	0	2	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	3	0	0
T199	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38016723	127	0	0
StatusRise_A	38016723	127	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	127	0	0
T29	1111	3	0	0
T30	1397	0	0	0
T31	2924	0	0	0
T32	1677	0	0	0
T33	1440	0	0	0
T34	2557	0	0	0
T53	0	2	0	0
T79	1276	1	0	0
T80	1499	3	0	0
T82	1931	0	0	0
T84	1990	0	0	0
T94	0	5	0	0
T98	0	1	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	2	0	0
T199	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38016723	127	0	0
T29	1111	3	0	0
T30	1397	0	0	0
T31	2924	0	0	0
T32	1677	0	0	0
T33	1440	0	0	0
T34	2557	0	0	0
T53	0	2	0	0
T79	1276	1	0	0
T80	1499	3	0	0
T82	1931	0	0	0
T84	1990	0	0	0
T94	0	5	0	0
T98	0	1	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	2	0	0
T199	0	2	0	0