Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	961029476	32870	0	0
CgEnOn_A	961029476	23537	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	961029476	32870	0	0
T4	12392	3	0	0
T5	43423	7	0	0
T6	49407	44	0	0
T28	8146	3	0	0
T29	44372	29	0	0
T30	53638	6	0	0
T31	31702	3	0	0
T32	42198	3	0	0
T33	67496	6	0	0
T34	28496	3	0	0
T53	0	5	0	0
T79	5810	12	0	0
T80	6475	18	0	0
T82	17045	1	0	0
T84	38351	0	0	0
T94	0	25	0	0
T98	0	10	0	0
T157	0	11	0	0
T196	0	5	0	0
T197	0	10	0	0
T198	0	15	0	0
T199	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	961029476	23537	0	0
T5	43423	4	0	0
T6	49407	41	0	0
T28	8146	0	0	0
T29	44372	26	0	0
T30	53638	3	0	0
T31	31702	0	0	0
T32	42198	0	0	0
T33	67496	3	0	0
T34	28496	0	0	0
T53	0	5	0	0
T79	5810	18	0	0
T80	6475	27	0	0
T82	21254	4	0	0
T83	0	3	0	0
T84	38351	0	0	0
T91	0	31	0	0
T92	0	14	0	0
T94	0	30	0	0
T98	0	10	0	0
T133	0	38	0	0
T157	0	11	0	0
T158	0	7	0	0
T196	0	5	0	0
T197	0	10	0	0
T198	0	15	0	0
T199	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	40333590	139	0	0
CgEnOn_A	40333590	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40333590	139	0	0
T29	1875	3	0	0
T30	2334	0	0	0
T31	1436	0	0	0
T32	2798	0	0	0
T33	2973	0	0	0
T34	1393	0	0	0
T53	0	1	0	0
T79	558	2	0	0
T80	670	3	0	0
T82	895	0	0	0
T84	3928	0	0	0
T94	0	5	0	0
T98	0	2	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	3	0	0
T199	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40333590	139	0	0
T29	1875	3	0	0
T30	2334	0	0	0
T31	1436	0	0	0
T32	2798	0	0	0
T33	2973	0	0	0
T34	1393	0	0	0
T53	0	1	0	0
T79	558	2	0	0
T80	670	3	0	0
T82	895	0	0	0
T84	3928	0	0	0
T94	0	5	0	0
T98	0	2	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	3	0	0
T199	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	20166389	139	0	0
CgEnOn_A	20166389	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20166389	139	0	0
T29	938	3	0	0
T30	1167	0	0	0
T31	716	0	0	0
T32	1398	0	0	0
T33	1486	0	0	0
T34	695	0	0	0
T53	0	1	0	0
T79	279	2	0	0
T80	335	3	0	0
T82	448	0	0	0
T84	1964	0	0	0
T94	0	5	0	0
T98	0	2	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	3	0	0
T199	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20166389	139	0	0
T29	938	3	0	0
T30	1167	0	0	0
T31	716	0	0	0
T32	1398	0	0	0
T33	1486	0	0	0
T34	695	0	0	0
T53	0	1	0	0
T79	279	2	0	0
T80	335	3	0	0
T82	448	0	0	0
T84	1964	0	0	0
T94	0	5	0	0
T98	0	2	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	3	0	0
T199	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	20166389	139	0	0
CgEnOn_A	20166389	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20166389	139	0	0
T29	938	3	0	0
T30	1167	0	0	0
T31	716	0	0	0
T32	1398	0	0	0
T33	1486	0	0	0
T34	695	0	0	0
T53	0	1	0	0
T79	279	2	0	0
T80	335	3	0	0
T82	448	0	0	0
T84	1964	0	0	0
T94	0	5	0	0
T98	0	2	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	3	0	0
T199	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20166389	139	0	0
T29	938	3	0	0
T30	1167	0	0	0
T31	716	0	0	0
T32	1398	0	0	0
T33	1486	0	0	0
T34	695	0	0	0
T53	0	1	0	0
T79	279	2	0	0
T80	335	3	0	0
T82	448	0	0	0
T84	1964	0	0	0
T94	0	5	0	0
T98	0	2	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	3	0	0
T199	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	20166389	139	0	0
CgEnOn_A	20166389	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20166389	139	0	0
T29	938	3	0	0
T30	1167	0	0	0
T31	716	0	0	0
T32	1398	0	0	0
T33	1486	0	0	0
T34	695	0	0	0
T53	0	1	0	0
T79	279	2	0	0
T80	335	3	0	0
T82	448	0	0	0
T84	1964	0	0	0
T94	0	5	0	0
T98	0	2	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	3	0	0
T199	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20166389	139	0	0
T29	938	3	0	0
T30	1167	0	0	0
T31	716	0	0	0
T32	1398	0	0	0
T33	1486	0	0	0
T34	695	0	0	0
T53	0	1	0	0
T79	279	2	0	0
T80	335	3	0	0
T82	448	0	0	0
T84	1964	0	0	0
T94	0	5	0	0
T98	0	2	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	3	0	0
T199	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	82648253	139	0	0
CgEnOn_A	82648253	128	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82648253	139	0	0
T29	3857	3	0	0
T30	4789	0	0	0
T31	2808	0	0	0
T32	3352	0	0	0
T33	6011	0	0	0
T34	2479	0	0	0
T53	0	1	0	0
T79	1236	2	0	0
T80	1364	3	0	0
T82	1911	0	0	0
T84	7962	0	0	0
T94	0	5	0	0
T98	0	2	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	3	0	0
T199	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82648253	128	0	0
T29	3857	3	0	0
T30	4789	0	0	0
T31	2808	0	0	0
T32	3352	0	0	0
T33	6011	0	0	0
T34	2479	0	0	0
T53	0	1	0	0
T79	1236	2	0	0
T80	1364	3	0	0
T82	1911	0	0	0
T84	7962	0	0	0
T94	0	5	0	0
T98	0	2	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	3	0	0
T199	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91151739	140	0	0
CgEnOn_A	91151739	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91151739	140	0	0
T29	4210	2	0	0
T30	4989	0	0	0
T31	2924	0	0	0
T32	3492	0	0	0
T33	6262	0	0	0
T34	2582	0	0	0
T53	0	1	0	0
T79	1291	2	0	0
T80	1375	3	0	0
T82	1990	0	0	0
T84	8294	0	0	0
T94	0	5	0	0
T98	0	1	0	0
T196	0	1	0	0
T197	0	3	0	0
T198	0	4	0	0
T199	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91151739	135	0	0
T29	4210	2	0	0
T30	4989	0	0	0
T31	2924	0	0	0
T32	3492	0	0	0
T33	6262	0	0	0
T34	2582	0	0	0
T53	0	1	0	0
T79	1291	2	0	0
T80	1375	3	0	0
T82	1990	0	0	0
T84	8294	0	0	0
T94	0	5	0	0
T98	0	1	0	0
T196	0	1	0	0
T197	0	3	0	0
T198	0	4	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91151739	140	0	0
CgEnOn_A	91151739	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91151739	140	0	0
T29	4210	2	0	0
T30	4989	0	0	0
T31	2924	0	0	0
T32	3492	0	0	0
T33	6262	0	0	0
T34	2582	0	0	0
T53	0	1	0	0
T79	1291	2	0	0
T80	1375	3	0	0
T82	1990	0	0	0
T84	8294	0	0	0
T94	0	5	0	0
T98	0	1	0	0
T196	0	1	0	0
T197	0	3	0	0
T198	0	4	0	0
T199	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91151739	135	0	0
T29	4210	2	0	0
T30	4989	0	0	0
T31	2924	0	0	0
T32	3492	0	0	0
T33	6262	0	0	0
T34	2582	0	0	0
T53	0	1	0	0
T79	1291	2	0	0
T80	1375	3	0	0
T82	1990	0	0	0
T84	8294	0	0	0
T94	0	5	0	0
T98	0	1	0	0
T196	0	1	0	0
T197	0	3	0	0
T198	0	4	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	43744900	128	0	0
CgEnOn_A	43744900	127	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43744900	128	0	0
T29	1948	3	0	0
T30	2395	0	0	0
T31	1403	0	0	0
T32	1677	0	0	0
T33	3006	0	0	0
T34	1240	0	0	0
T53	0	2	0	0
T79	597	1	0	0
T80	686	3	0	0
T82	955	0	0	0
T84	3981	0	0	0
T94	0	5	0	0
T98	0	1	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	2	0	0
T199	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43744900	127	0	0
T29	1948	3	0	0
T30	2395	0	0	0
T31	1403	0	0	0
T32	1677	0	0	0
T33	3006	0	0	0
T34	1240	0	0	0
T53	0	2	0	0
T79	597	1	0	0
T80	686	3	0	0
T82	955	0	0	0
T84	3981	0	0	0
T94	0	5	0	0
T98	0	1	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	2	0	0
T199	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	20166389	5516	0	0
CgEnOn_A	20166389	3199	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20166389	5516	0	0
T4	1491	1	0	0
T5	1665	2	0	0
T6	1913	14	0	0
T28	300	1	0	0
T29	938	4	0	0
T30	1167	1	0	0
T31	716	1	0	0
T32	1398	1	0	0
T33	1486	1	0	0
T34	695	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20166389	3199	0	0
T5	1665	1	0	0
T6	1913	13	0	0
T28	300	0	0	0
T29	938	3	0	0
T30	1167	0	0	0
T31	716	0	0	0
T32	1398	0	0	0
T33	1486	0	0	0
T34	695	0	0	0
T79	0	2	0	0
T80	0	3	0	0
T82	448	1	0	0
T91	0	10	0	0
T92	0	4	0	0
T94	0	5	0	0
T133	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	40333590	5510	0	0
CgEnOn_A	40333590	3193	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40333590	5510	0	0
T4	2982	1	0	0
T5	3330	2	0	0
T6	3827	15	0	0
T28	600	1	0	0
T29	1875	4	0	0
T30	2334	1	0	0
T31	1436	1	0	0
T32	2798	1	0	0
T33	2973	1	0	0
T34	1393	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40333590	3193	0	0
T5	3330	1	0	0
T6	3827	14	0	0
T28	600	0	0	0
T29	1875	3	0	0
T30	2334	0	0	0
T31	1436	0	0	0
T32	2798	0	0	0
T33	2973	0	0	0
T34	1393	0	0	0
T79	0	2	0	0
T80	0	3	0	0
T82	895	1	0	0
T83	0	1	0	0
T91	0	11	0	0
T92	0	5	0	0
T133	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	82648253	5539	0	0
CgEnOn_A	82648253	3211	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82648253	5539	0	0
T4	5279	1	0	0
T5	6781	2	0	0
T6	7706	15	0	0
T28	1279	1	0	0
T29	3857	4	0	0
T30	4789	1	0	0
T31	2808	1	0	0
T32	3352	1	0	0
T33	6011	1	0	0
T34	2479	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82648253	3211	0	0
T5	6781	1	0	0
T6	7706	14	0	0
T28	1279	0	0	0
T29	3857	3	0	0
T30	4789	0	0	0
T31	2808	0	0	0
T32	3352	0	0	0
T33	6011	0	0	0
T34	2479	0	0	0
T79	0	2	0	0
T80	0	3	0	0
T82	1911	1	0	0
T83	0	1	0	0
T91	0	10	0	0
T92	0	5	0	0
T133	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	43744900	5521	0	0
CgEnOn_A	43744900	3192	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43744900	5521	0	0
T4	2640	1	0	0
T5	3391	2	0	0
T6	3853	14	0	0
T28	639	1	0	0
T29	1948	4	0	0
T30	2395	1	0	0
T31	1403	1	0	0
T32	1677	1	0	0
T33	3006	1	0	0
T34	1240	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43744900	3192	0	0
T5	3391	1	0	0
T6	3853	13	0	0
T28	639	0	0	0
T29	1948	3	0	0
T30	2395	0	0	0
T31	1403	0	0	0
T32	1677	0	0	0
T33	3006	0	0	0
T34	1240	0	0	0
T79	0	1	0	0
T80	0	3	0	0
T82	955	1	0	0
T83	0	1	0	0
T91	0	10	0	0
T92	0	4	0	0
T133	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Covered	T5,T30,T33
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91151739	2427	0	0
CgEnOn_A	91151739	2422	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91151739	2427	0	0
T5	7064	1	0	0
T6	8027	0	0	0
T28	1332	0	0	0
T29	4210	2	0	0
T30	4989	3	0	0
T31	2924	0	0	0
T32	3492	0	0	0
T33	6262	3	0	0
T34	2582	0	0	0
T79	0	2	0	0
T80	0	3	0	0
T82	1990	1	0	0
T83	0	1	0	0
T157	0	11	0	0
T158	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91151739	2422	0	0
T5	7064	1	0	0
T6	8027	0	0	0
T28	1332	0	0	0
T29	4210	2	0	0
T30	4989	3	0	0
T31	2924	0	0	0
T32	3492	0	0	0
T33	6262	3	0	0
T34	2582	0	0	0
T79	0	2	0	0
T80	0	3	0	0
T82	1990	1	0	0
T83	0	1	0	0
T157	0	11	0	0
T158	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Covered	T5,T30,T33
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91151739	2456	0	0
CgEnOn_A	91151739	2451	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91151739	2456	0	0
T5	7064	1	0	0
T6	8027	0	0	0
T28	1332	0	0	0
T29	4210	2	0	0
T30	4989	4	0	0
T31	2924	0	0	0
T32	3492	0	0	0
T33	6262	4	0	0
T34	2582	0	0	0
T79	0	2	0	0
T80	0	3	0	0
T82	1990	1	0	0
T83	0	1	0	0
T157	0	9	0	0
T158	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91151739	2451	0	0
T5	7064	1	0	0
T6	8027	0	0	0
T28	1332	0	0	0
T29	4210	2	0	0
T30	4989	4	0	0
T31	2924	0	0	0
T32	3492	0	0	0
T33	6262	4	0	0
T34	2582	0	0	0
T79	0	2	0	0
T80	0	3	0	0
T82	1990	1	0	0
T83	0	1	0	0
T157	0	9	0	0
T158	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Covered	T5,T30,T33
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91151739	2423	0	0
CgEnOn_A	91151739	2418	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91151739	2423	0	0
T5	7064	1	0	0
T6	8027	0	0	0
T28	1332	0	0	0
T29	4210	2	0	0
T30	4989	4	0	0
T31	2924	0	0	0
T32	3492	0	0	0
T33	6262	1	0	0
T34	2582	0	0	0
T79	0	2	0	0
T80	0	3	0	0
T82	1990	1	0	0
T83	0	1	0	0
T157	0	9	0	0
T158	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91151739	2418	0	0
T5	7064	1	0	0
T6	8027	0	0	0
T28	1332	0	0	0
T29	4210	2	0	0
T30	4989	4	0	0
T31	2924	0	0	0
T32	3492	0	0	0
T33	6262	1	0	0
T34	2582	0	0	0
T79	0	2	0	0
T80	0	3	0	0
T82	1990	1	0	0
T83	0	1	0	0
T157	0	9	0	0
T158	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T79,T80
1	0	Covered	T5,T30,T33
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91151739	2375	0	0
CgEnOn_A	91151739	2370	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91151739	2375	0	0
T5	7064	1	0	0
T6	8027	0	0	0
T28	1332	0	0	0
T29	4210	2	0	0
T30	4989	4	0	0
T31	2924	0	0	0
T32	3492	0	0	0
T33	6262	2	0	0
T34	2582	0	0	0
T79	0	2	0	0
T80	0	3	0	0
T82	1990	1	0	0
T83	0	1	0	0
T157	0	9	0	0
T158	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91151739	2370	0	0
T5	7064	1	0	0
T6	8027	0	0	0
T28	1332	0	0	0
T29	4210	2	0	0
T30	4989	4	0	0
T31	2924	0	0	0
T32	3492	0	0	0
T33	6262	2	0	0
T34	2582	0	0	0
T79	0	2	0	0
T80	0	3	0	0
T82	1990	1	0	0
T83	0	1	0	0
T157	0	9	0	0
T158	0	6	0	0