Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	202354	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

459735

1

T4

9

T5

29

T6

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	193540	1			T4	7		T5	42		T6	7
values[0x0]	221814	1			T4	8		T5	28		T6	8
values[0x1]	246735	1			T4	7		T5	11		T6	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	140515	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

521574

1

T4

10

T5

36

T6

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2623	1			T20	3		T9	4		T36	3
valid_sources[0x01]	2634	1			T29	7		T88	1		T113	2
valid_sources[0x02]	2307	1			T128	1		T113	3		T3	1
valid_sources[0x03]	2917	1			T27	1		T89	63		T128	1
valid_sources[0x04]	2578	1			T62	92		T113	1		T9	1
valid_sources[0x05]	2319	1			T27	1		T88	4		T101	1
valid_sources[0x06]	3248	1			T88	1		T74	1		T44	1
valid_sources[0x07]	3296	1			T3	4		T21	940		T9	1
valid_sources[0x08]	2551	1			T27	1		T113	2		T3	1
valid_sources[0x09]	2135	1			T22	5		T36	1		T30	12
valid_sources[0x0a]	1944	1			T49	1		T20	1		T9	1
valid_sources[0x0b]	2394	1			T88	1		T154	5		T3	2
valid_sources[0x0c]	3972	1			T27	1		T59	1		T113	4
valid_sources[0x0d]	2553	1			T4	1		T74	1		T101	2
valid_sources[0x0e]	2565	1			T27	1		T128	6		T3	4
valid_sources[0x0f]	1949	1			T29	4		T126	1		T9	1
valid_sources[0x10]	2573	1			T58	1		T60	1		T3	1
valid_sources[0x11]	2627	1			T3	2		T9	1		T22	3
valid_sources[0x12]	2305	1			T27	1		T47	1		T58	1
valid_sources[0x13]	2378	1			T88	5		T113	1		T3	2
valid_sources[0x14]	3162	1			T88	1		T47	1		T3	5
valid_sources[0x15]	2627	1			T74	2		T58	1		T49	6
valid_sources[0x16]	2220	1			T113	1		T3	2		T9	2
valid_sources[0x17]	2863	1			T126	1		T58	1		T59	1
valid_sources[0x18]	2800	1			T47	2		T3	4		T9	2
valid_sources[0x19]	2692	1			T49	2		T59	1		T3	6
valid_sources[0x1a]	2614	1			T88	1		T127	2		T44	1
valid_sources[0x1b]	2594	1			T102	2		T58	2		T3	2
valid_sources[0x1c]	2749	1			T55	2		T47	2		T126	1
valid_sources[0x1d]	2600	1			T3	3		T9	1		T22	1
valid_sources[0x1e]	2972	1			T44	2		T3	3		T20	15
valid_sources[0x1f]	2452	1			T27	1		T74	1		T101	1
valid_sources[0x20]	2647	1			T74	1		T44	2		T49	2
valid_sources[0x21]	2025	1			T27	2		T3	2		T22	2
valid_sources[0x22]	2114	1			T27	1		T49	2		T18	22
valid_sources[0x23]	2800	1			T29	3		T101	1		T3	2
valid_sources[0x24]	2219	1			T101	1		T58	1		T3	2
valid_sources[0x25]	2911	1			T127	2		T22	2		T32	2
valid_sources[0x26]	1927	1			T47	3		T3	4		T30	12
valid_sources[0x27]	1959	1			T5	30		T58	3		T3	3
valid_sources[0x28]	3391	1			T101	2		T47	1		T3	3
valid_sources[0x29]	2601	1			T127	4		T126	1		T49	1
valid_sources[0x2a]	2850	1			T27	4		T47	2		T59	1
valid_sources[0x2b]	2233	1			T29	2		T36	2		T30	21
valid_sources[0x2c]	2144	1			T9	2		T22	4		T30	13
valid_sources[0x2d]	2752	1			T44	2		T60	1		T3	4
valid_sources[0x2e]	2401	1			T27	1		T88	1		T3	1
valid_sources[0x2f]	2029	1			T27	2		T126	1		T3	1
valid_sources[0x30]	2190	1			T29	6		T49	1		T3	1
valid_sources[0x31]	3150	1			T88	1		T128	3		T3	3
valid_sources[0x32]	2323	1			T102	3		T113	1		T3	1
valid_sources[0x33]	3769	1			T88	1		T101	1		T36	1
valid_sources[0x34]	2400	1			T49	1		T3	1		T20	10
valid_sources[0x35]	2064	1			T101	2		T44	2		T3	2
valid_sources[0x36]	2560	1			T27	8		T3	2		T20	1
valid_sources[0x37]	2377	1			T101	1		T127	2		T47	1
valid_sources[0x38]	2299	1			T60	1		T18	13		T3	3
valid_sources[0x39]	2589	1			T6	22		T126	1		T9	1
valid_sources[0x3a]	3025	1			T58	1		T128	2		T18	1
valid_sources[0x3b]	2618	1			T29	2		T88	3		T74	2
valid_sources[0x3c]	2838	1			T27	1		T88	2		T47	4
valid_sources[0x3d]	2663	1			T126	3		T113	2		T18	4
valid_sources[0x3e]	2283	1			T88	1		T3	7		T9	1
valid_sources[0x3f]	2574	1			T88	1		T9	1		T22	1
valid_sources[0x40]	2678	1			T27	4		T3	4		T32	10
valid_sources[0x41]	3625	1			T4	2		T88	2		T3	1
valid_sources[0x42]	2136	1			T44	2		T3	1		T22	3
valid_sources[0x43]	3110	1			T101	1		T2	611		T3	3
valid_sources[0x44]	2732	1			T47	1		T58	2		T3	1
valid_sources[0x45]	2023	1			T88	3		T113	5		T1	124
valid_sources[0x46]	4535	1			T27	1		T3	6		T9	3
valid_sources[0x47]	2262	1			T88	3		T102	3		T50	2
valid_sources[0x48]	2737	1			T55	1		T113	4		T3	5
valid_sources[0x49]	2919	1			T5	21		T49	1		T50	1
valid_sources[0x4a]	4181	1			T4	1		T55	4		T74	1
valid_sources[0x4b]	2195	1			T27	1		T127	1		T58	1
valid_sources[0x4c]	2381	1			T101	3		T44	2		T19	1
valid_sources[0x4d]	2930	1			T88	2		T22	1		T36	1
valid_sources[0x4e]	2613	1			T74	1		T9	1		T22	4
valid_sources[0x4f]	2548	1			T3	2		T20	1		T22	3
valid_sources[0x50]	2146	1			T27	2		T29	13		T102	2
valid_sources[0x51]	2101	1			T29	4		T88	2		T47	1
valid_sources[0x52]	2961	1			T5	9		T88	1		T101	1
valid_sources[0x53]	2445	1			T88	1		T127	1		T44	1
valid_sources[0x54]	1744	1			T74	1		T3	1		T9	3
valid_sources[0x55]	2300	1			T27	1		T58	2		T113	2
valid_sources[0x56]	2096	1			T27	2		T101	1		T44	2
valid_sources[0x57]	2331	1			T126	1		T3	1		T32	119
valid_sources[0x58]	2519	1			T74	1		T101	1		T113	2
valid_sources[0x59]	2008	1			T47	2		T128	2		T113	1
valid_sources[0x5a]	2850	1			T4	7		T127	2		T58	2
valid_sources[0x5b]	2805	1			T9	1		T30	11		T90	1
valid_sources[0x5c]	3303	1			T29	3		T101	1		T47	7
valid_sources[0x5d]	1907	1			T59	2		T3	2		T36	1
valid_sources[0x5e]	2288	1			T58	1		T60	1		T113	1
valid_sources[0x5f]	2379	1			T44	1		T3	1		T9	3
valid_sources[0x60]	2452	1			T9	4		T22	1		T36	2
valid_sources[0x61]	2588	1			T55	2		T58	1		T22	2
valid_sources[0x62]	2396	1			T49	1		T113	1		T3	2
valid_sources[0x63]	2412	1			T3	2		T9	2		T22	1
valid_sources[0x64]	2931	1			T127	1		T44	1		T49	1
valid_sources[0x65]	2612	1			T26	4		T28	13		T127	3
valid_sources[0x66]	2601	1			T102	2		T3	1		T36	2
valid_sources[0x67]	2281	1			T88	2		T3	2		T20	18
valid_sources[0x68]	2809	1			T4	2		T27	1		T47	2
valid_sources[0x69]	2059	1			T18	26		T19	3		T20	1
valid_sources[0x6a]	2090	1			T47	5		T58	2		T3	3
valid_sources[0x6b]	2707	1			T127	1		T49	1		T3	2
valid_sources[0x6c]	2959	1			T59	1		T3	3		T22	2
valid_sources[0x6d]	2780	1			T88	1		T74	1		T3	3
valid_sources[0x6e]	2680	1			T127	1		T47	1		T9	1
valid_sources[0x6f]	3332	1			T27	1		T19	13		T22	2
valid_sources[0x70]	2726	1			T59	2		T3	4		T20	6
valid_sources[0x71]	2490	1			T55	1		T113	3		T3	1
valid_sources[0x72]	2598	1			T74	1		T49	1		T3	2
valid_sources[0x73]	2103	1			T3	1		T9	2		T30	8
valid_sources[0x74]	2332	1			T102	8		T50	3		T154	1
valid_sources[0x75]	2342	1			T27	1		T101	1		T44	1
valid_sources[0x76]	2064	1			T26	4		T59	3		T60	1
valid_sources[0x77]	2819	1			T29	8		T9	1		T22	1
valid_sources[0x78]	2287	1			T47	1		T22	3		T36	2
valid_sources[0x79]	3229	1			T101	1		T3	3		T9	1
valid_sources[0x7a]	2779	1			T74	1		T9	2		T22	5
valid_sources[0x7b]	2804	1			T47	1		T58	2		T61	1
valid_sources[0x7c]	2249	1			T44	1		T58	1		T113	1
valid_sources[0x7d]	2858	1			T3	1		T9	2		T22	2
valid_sources[0x7e]	2536	1			T88	3		T101	1		T3	1
valid_sources[0x7f]	2369	1			T88	1		T113	2		T3	6
valid_sources[0x80]	2459	1			T126	1		T44	1		T59	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

128731

1

T4

4

T5

24

T6

6

values[0x0]

all_enables

biggest_size

177537

1

T4

2

T5

4

T6

1

values[0x1]

all_enables

biggest_size

153467

1

T4

3

T5

1

T6

1