Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T23,T25
0	1	Covered	T25,T74,T60
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T74
1	0	Covered	T23,T45,T46
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	186350209	7844	0	0
GateOpen_A	186350209	14295	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186350209	7844	0	0
T5	5452	4	0	0
T6	3920	0	0	0
T23	8822	20	0	0
T24	3297	0	0	0
T25	23390	37	0	0
T26	3933	0	0	0
T27	6203	0	0	0
T28	9219	0	0	0
T29	6905	0	0	0
T32	0	12	0	0
T45	0	9	0	0
T46	0	12	0	0
T47	0	4	0	0
T48	0	4	0	0
T55	21495	0	0	0
T60	0	4	0	0
T74	0	32	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186350209	14295	0	0
T5	5452	8	0	0
T6	3920	4	0	0
T23	8822	24	0	0
T24	3297	0	0	0
T25	23390	41	0	0
T26	3933	0	0	0
T27	6203	4	0	0
T28	9219	0	0	0
T29	6905	0	0	0
T47	0	4	0	0
T55	21495	0	0	0
T74	0	32	0	0
T89	0	4	0	0
T102	0	4	0	0
T126	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T23,T25
0	1	Covered	T25,T74,T60
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T74
1	0	Covered	T23,T45,T46
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	20069211	1894	0	0
GateOpen_A	20069211	3504	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20069211	1894	0	0
T5	593	1	0	0
T6	451	0	0	0
T23	966	5	0	0
T24	356	0	0	0
T25	2577	9	0	0
T26	438	0	0	0
T27	681	0	0	0
T28	1016	0	0	0
T29	757	0	0	0
T32	0	3	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	2495	0	0	0
T60	0	1	0	0
T74	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20069211	3504	0	0
T5	593	2	0	0
T6	451	1	0	0
T23	966	6	0	0
T24	356	0	0	0
T25	2577	10	0	0
T26	438	0	0	0
T27	681	1	0	0
T28	1016	0	0	0
T29	757	0	0	0
T47	0	1	0	0
T55	2495	0	0	0
T74	0	8	0	0
T89	0	1	0	0
T102	0	1	0	0
T126	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T23,T25
0	1	Covered	T25,T74,T60
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T74
1	0	Covered	T23,T45,T46
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	40138681	1978	0	0
GateOpen_A	40138681	3588	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40138681	1978	0	0
T5	1185	1	0	0
T6	901	0	0	0
T23	1931	5	0	0
T24	711	0	0	0
T25	5153	10	0	0
T26	876	0	0	0
T27	1361	0	0	0
T28	2031	0	0	0
T29	1513	0	0	0
T32	0	3	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	4990	0	0	0
T60	0	1	0	0
T74	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40138681	3588	0	0
T5	1185	2	0	0
T6	901	1	0	0
T23	1931	6	0	0
T24	711	0	0	0
T25	5153	11	0	0
T26	876	0	0	0
T27	1361	1	0	0
T28	2031	0	0	0
T29	1513	0	0	0
T47	0	1	0	0
T55	4990	0	0	0
T74	0	7	0	0
T89	0	1	0	0
T102	0	1	0	0
T126	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T23,T25
0	1	Covered	T25,T74,T60
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T74
1	0	Covered	T23,T45,T46
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	82314562	2004	0	0
GateOpen_A	82314562	3619	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82314562	2004	0	0
T5	2449	1	0	0
T6	1712	0	0	0
T23	3941	5	0	0
T24	1487	0	0	0
T25	10440	8	0	0
T26	1746	0	0	0
T27	2774	0	0	0
T28	4114	0	0	0
T29	3090	0	0	0
T32	0	3	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9340	0	0	0
T60	0	1	0	0
T74	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82314562	3619	0	0
T5	2449	2	0	0
T6	1712	1	0	0
T23	3941	6	0	0
T24	1487	0	0	0
T25	10440	9	0	0
T26	1746	0	0	0
T27	2774	1	0	0
T28	4114	0	0	0
T29	3090	0	0	0
T47	0	1	0	0
T55	9340	0	0	0
T74	0	9	0	0
T89	0	1	0	0
T102	0	1	0	0
T126	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T23,T25
0	1	Covered	T25,T74,T60
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T74
1	0	Covered	T23,T45,T46
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	43827755	1968	0	0
GateOpen_A	43827755	3584	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43827755	1968	0	0
T5	1225	1	0	0
T6	856	0	0	0
T23	1984	5	0	0
T24	743	0	0	0
T25	5220	10	0	0
T26	873	0	0	0
T27	1387	0	0	0
T28	2058	0	0	0
T29	1545	0	0	0
T32	0	3	0	0
T45	0	3	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	4670	0	0	0
T60	0	1	0	0
T74	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43827755	3584	0	0
T5	1225	2	0	0
T6	856	1	0	0
T23	1984	6	0	0
T24	743	0	0	0
T25	5220	11	0	0
T26	873	0	0	0
T27	1387	1	0	0
T28	2058	0	0	0
T29	1545	0	0	0
T47	0	1	0	0
T55	4670	0	0	0
T74	0	8	0	0
T89	0	1	0	0
T102	0	1	0	0
T126	0	1	0	0