Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	183747910	31976	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	183747910	31976	0	0
T1	66390	39	0	0
T2	239450	0	0	0
T3	413090	0	0	0
T9	367175	62	0	0
T10	274715	282	0	0
T11	0	152	0	0
T12	0	128	0	0
T13	0	54	0	0
T14	0	177	0	0
T15	0	192	0	0
T16	0	286	0	0
T17	0	387	0	0
T18	70000	0	0	0
T19	60845	0	0	0
T20	270650	0	0	0
T21	557505	0	0	0
T22	647675	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	36749582	4773	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	4773	0	0
T1	13278	6	0	0
T2	47890	0	0	0
T3	82618	0	0	0
T9	73435	9	0	0
T10	54943	46	0	0
T11	0	25	0	0
T12	0	18	0	0
T13	0	9	0	0
T14	0	28	0	0
T15	0	31	0	0
T16	0	46	0	0
T17	0	55	0	0
T18	14000	0	0	0
T19	12169	0	0	0
T20	54130	0	0	0
T21	111501	0	0	0
T22	129535	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	36749582	4703	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	4703	0	0
T1	13278	6	0	0
T2	47890	0	0	0
T3	82618	0	0	0
T9	73435	9	0	0
T10	54943	46	0	0
T11	0	24	0	0
T12	0	18	0	0
T13	0	8	0	0
T14	0	28	0	0
T15	0	31	0	0
T16	0	46	0	0
T17	0	56	0	0
T18	14000	0	0	0
T19	12169	0	0	0
T20	54130	0	0	0
T21	111501	0	0	0
T22	129535	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	36749582	6426	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	6426	0	0
T1	13278	8	0	0
T2	47890	0	0	0
T3	82618	0	0	0
T9	73435	14	0	0
T10	54943	57	0	0
T11	0	30	0	0
T12	0	25	0	0
T13	0	11	0	0
T14	0	36	0	0
T15	0	39	0	0
T16	0	58	0	0
T17	0	78	0	0
T18	14000	0	0	0
T19	12169	0	0	0
T20	54130	0	0	0
T21	111501	0	0	0
T22	129535	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	36749582	6426	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	6426	0	0
T1	13278	8	0	0
T2	47890	0	0	0
T3	82618	0	0	0
T9	73435	12	0	0
T10	54943	57	0	0
T11	0	31	0	0
T12	0	25	0	0
T13	0	11	0	0
T14	0	36	0	0
T15	0	39	0	0
T16	0	58	0	0
T17	0	76	0	0
T18	14000	0	0	0
T19	12169	0	0	0
T20	54130	0	0	0
T21	111501	0	0	0
T22	129535	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	36749582	9648	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	9648	0	0
T1	13278	11	0	0
T2	47890	0	0	0
T3	82618	0	0	0
T9	73435	18	0	0
T10	54943	76	0	0
T11	0	42	0	0
T12	0	42	0	0
T13	0	15	0	0
T14	0	49	0	0
T15	0	52	0	0
T16	0	78	0	0
T17	0	122	0	0
T18	14000	0	0	0
T19	12169	0	0	0
T20	54130	0	0	0
T21	111501	0	0	0
T22	129535	0	0	0