Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

22                      
23         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T44,T18,T19

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	36749582	33930727	0	0
AllClkBypReqTrue_A	36749582	72948	0	0
IoClkBypReqFalse_A	36749582	33881534	0	2382
IoClkBypReqTrue_A	36749582	117547	0	0
LcClkBypAckFalse_A	36749582	33935479	0	0
LcClkBypAckTrue_A	36749582	68196	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	33930727	0	0
T4	1806	1420	0	0
T5	2501	2292	0	0
T6	1729	1491	0	0
T23	1197	1157	0	0
T24	1548	1358	0	0
T25	761	746	0	0
T26	1782	1478	0	0
T27	2745	2665	0	0
T28	1200	1152	0	0
T29	3218	3034	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	72948	0	0
T4	1806	119	0	0
T5	2501	0	0	0
T6	1729	129	0	0
T23	1197	0	0	0
T24	1548	20	0	0
T25	761	0	0	0
T26	1782	110	0	0
T27	2745	0	0	0
T28	1200	0	0	0
T29	3218	0	0	0
T58	0	210	0	0
T59	0	91	0	0
T101	0	213	0	0
T102	0	104	0	0
T114	0	191	0	0
T126	0	18	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	33881534	0	2382
T4	1806	1394	0	3
T5	2501	2290	0	3
T6	1729	1392	0	3
T23	1197	1155	0	3
T24	1548	1376	0	3
T25	761	744	0	3
T26	1782	1444	0	3
T27	2745	2663	0	3
T28	1200	1150	0	3
T29	3218	3032	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	117547	0	0
T4	1806	143	0	0
T5	2501	0	0	0
T6	1729	226	0	0
T23	1197	0	0	0
T24	1548	0	0	0
T25	761	0	0	0
T26	1782	142	0	0
T27	2745	0	0	0
T28	1200	0	0	0
T29	3218	0	0	0
T55	0	88	0	0
T59	0	114	0	0
T61	0	91	0	0
T101	0	410	0	0
T102	0	202	0	0
T114	0	335	0	0
T126	0	256	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	33935479	0	0
T4	1806	1447	0	0
T5	2501	2292	0	0
T6	1729	1512	0	0
T23	1197	1157	0	0
T24	1548	1378	0	0
T25	761	746	0	0
T26	1782	1489	0	0
T27	2745	2665	0	0
T28	1200	1152	0	0
T29	3218	3034	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	68196	0	0
T4	1806	92	0	0
T5	2501	0	0	0
T6	1729	108	0	0
T23	1197	0	0	0
T24	1548	0	0	0
T25	761	0	0	0
T26	1782	99	0	0
T27	2745	0	0	0
T28	1200	0	0	0
T29	3218	0	0	0
T55	0	74	0	0
T59	0	98	0	0
T61	0	50	0	0
T101	0	113	0	0
T102	0	127	0	0
T114	0	145	0	0
T126	0	139	0	0