Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	364923468	9320	0	0
TransStop_A	364923468	4821	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364923468	9320	0	0
T5	10208	4	0	0
T6	7132	0	0	0
T23	16436	0	0	0
T24	6196	0	0	0
T25	43500	0	0	0
T26	7272	0	0	0
T27	11556	26	0	0
T28	17144	0	0	0
T29	12876	33	0	0
T47	0	4	0	0
T48	0	4	0	0
T55	38916	0	0	0
T62	0	27	0	0
T88	0	27	0	0
T89	0	18	0	0
T127	0	12	0	0
T128	0	12	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	364923468	4821	0	0
T5	10208	4	0	0
T6	7132	0	0	0
T23	16436	0	0	0
T24	6196	0	0	0
T25	43500	0	0	0
T26	7272	0	0	0
T27	11556	17	0	0
T28	17144	0	0	0
T29	12876	17	0	0
T47	0	4	0	0
T48	0	4	0	0
T55	38916	0	0	0
T62	0	13	0	0
T88	0	10	0	0
T89	0	4	0	0
T113	0	4	0	0
T127	0	4	0	0
T128	0	10	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	91230867	2290	0	0
TransStop_A	91230867	1206	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230867	2290	0	0
T5	2552	1	0	0
T6	1783	0	0	0
T23	4109	0	0	0
T24	1549	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	6	0	0
T28	4286	0	0	0
T29	3219	9	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9729	0	0	0
T62	0	6	0	0
T88	0	5	0	0
T89	0	4	0	0
T127	0	3	0	0
T128	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230867	1206	0	0
T5	2552	1	0	0
T6	1783	0	0	0
T23	4109	0	0	0
T24	1549	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	4	0	0
T28	4286	0	0	0
T29	3219	4	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9729	0	0	0
T62	0	3	0	0
T88	0	1	0	0
T89	0	1	0	0
T113	0	4	0	0
T128	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	91230867	2314	0	0
TransStop_A	91230867	1167	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230867	2314	0	0
T5	2552	1	0	0
T6	1783	0	0	0
T23	4109	0	0	0
T24	1549	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	4	0	0
T28	4286	0	0	0
T29	3219	9	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9729	0	0	0
T62	0	9	0	0
T88	0	7	0	0
T89	0	5	0	0
T127	0	4	0	0
T128	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230867	1167	0	0
T5	2552	1	0	0
T6	1783	0	0	0
T23	4109	0	0	0
T24	1549	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	2	0	0
T28	4286	0	0	0
T29	3219	4	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9729	0	0	0
T62	0	5	0	0
T88	0	1	0	0
T89	0	1	0	0
T127	0	2	0	0
T128	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	91230867	2321	0	0
TransStop_A	91230867	1218	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230867	2321	0	0
T5	2552	1	0	0
T6	1783	0	0	0
T23	4109	0	0	0
T24	1549	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	8	0	0
T28	4286	0	0	0
T29	3219	5	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9729	0	0	0
T62	0	7	0	0
T88	0	7	0	0
T89	0	4	0	0
T127	0	3	0	0
T128	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230867	1218	0	0
T5	2552	1	0	0
T6	1783	0	0	0
T23	4109	0	0	0
T24	1549	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	5	0	0
T28	4286	0	0	0
T29	3219	4	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9729	0	0	0
T62	0	2	0	0
T88	0	4	0	0
T89	0	1	0	0
T127	0	1	0	0
T128	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	91230867	2395	0	0
TransStop_A	91230867	1230	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230867	2395	0	0
T5	2552	1	0	0
T6	1783	0	0	0
T23	4109	0	0	0
T24	1549	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	8	0	0
T28	4286	0	0	0
T29	3219	10	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9729	0	0	0
T62	0	5	0	0
T88	0	8	0	0
T89	0	5	0	0
T127	0	2	0	0
T128	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230867	1230	0	0
T5	2552	1	0	0
T6	1783	0	0	0
T23	4109	0	0	0
T24	1549	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	6	0	0
T28	4286	0	0	0
T29	3219	5	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9729	0	0	0
T62	0	3	0	0
T88	0	4	0	0
T89	0	1	0	0
T127	0	1	0	0
T128	0	3	0	0