Unified Coverage Report :: Module :: prim_generic_clock_gating

Module : prim_generic_clock_gating

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_gating_0/rtl/prim_generic_clock_gating.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_main_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic	100.00	100.00	100.00			100.00
tb.dut.u_io_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic	100.00	100.00	100.00			100.00
tb.dut.u_io_div2_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic	100.00	100.00	100.00			100.00
tb.dut.u_io_div4_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic	100.00	100.00	100.00			100.00
tb.dut.u_usb_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic	100.00	100.00	100.00			100.00
tb.dut.u_clk_io_div4_peri_cg.gen_generic.u_impl_generic	100.00	100.00	100.00			100.00
tb.dut.u_clk_io_div2_peri_cg.gen_generic.u_impl_generic	100.00	100.00	100.00			100.00
tb.dut.u_clk_io_peri_cg.gen_generic.u_impl_generic	100.00	100.00	100.00			100.00
tb.dut.u_clk_usb_peri_cg.gen_generic.u_impl_generic	100.00	100.00	100.00			100.00
tb.dut.u_clk_main_aes_trans.u_cg.gen_generic.u_impl_generic	100.00	100.00	100.00			100.00
tb.dut.u_clk_main_hmac_trans.u_cg.gen_generic.u_impl_generic	100.00	100.00	100.00			100.00
tb.dut.u_clk_main_kmac_trans.u_cg.gen_generic.u_impl_generic	100.00	100.00	100.00			100.00
tb.dut.u_clk_main_otbn_trans.u_cg.gen_generic.u_impl_generic	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_main_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							i_cg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_io_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							i_cg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_io_div2_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							i_cg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_io_div4_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							i_cg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_usb_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							i_cg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_io_div4_peri_cg.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_io_div4_peri_cg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_io_div2_peri_cg.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_io_div2_peri_cg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_io_peri_cg.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_io_peri_cg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_usb_peri_cg.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_usb_peri_cg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_main_aes_trans.u_cg.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_cg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_main_hmac_trans.u_cg.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_cg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_main_kmac_trans.u_cg.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_cg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_clk_main_otbn_trans.u_cg.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_cg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_gating

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	22	2	2	100.00
CONT_ASSIGN	26	1	1	100.00

21                        always_latch begin
22         1/1              if (!clk_i) begin
           Tests:       T4 T5 T6 
23         1/1                en_latch = en_i | test_en_i;
           Tests:       T4 T5 T6 
24                          end
                        MISSING_ELSE
25                        end
26         1/1            assign clk_o = en_latch & clk_i;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : prim_generic_clock_gating

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T23
0	1	Covered	T4,T24,T25
1	0	Covered	T4,T5,T6

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Module : prim_generic_clock_gating

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	22	2	2	100.00

22             if (!clk_i) begin
               -1-  
23               en_latch = en_i | test_en_i;
                 ==>
24             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	22	2	2	100.00
CONT_ASSIGN	26	1	1	100.00

21                        always_latch begin
22         1/1              if (!clk_i) begin
           Tests:       T4 T5 T6 
23         1/1                en_latch = en_i | test_en_i;
           Tests:       T4 T5 T6 
24                          end
                        MISSING_ELSE
25                        end
26         1/1            assign clk_o = en_latch & clk_i;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_main_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T23
0	1	Covered	T4,T24,T26
1	0	Covered	T4,T5,T6

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_main_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	22	2	2	100.00

22             if (!clk_i) begin
               -1-  
23               en_latch = en_i | test_en_i;
                 ==>
24             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	22	2	2	100.00
CONT_ASSIGN	26	1	1	100.00

21                        always_latch begin
22         1/1              if (!clk_i) begin
           Tests:       T4 T5 T6 
23         1/1                en_latch = en_i | test_en_i;
           Tests:       T4 T5 T6 
24                          end
                        MISSING_ELSE
25                        end
26         1/1            assign clk_o = en_latch & clk_i;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_io_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T23
0	1	Covered	T4,T24,T26
1	0	Covered	T4,T5,T6

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_io_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	22	2	2	100.00

22             if (!clk_i) begin
               -1-  
23               en_latch = en_i | test_en_i;
                 ==>
24             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	22	2	2	100.00
CONT_ASSIGN	26	1	1	100.00

21                        always_latch begin
22         1/1              if (!clk_i) begin
           Tests:       T4 T5 T6 
23         1/1                en_latch = en_i | test_en_i;
           Tests:       T4 T5 T6 
24                          end
                        MISSING_ELSE
25                        end
26         1/1            assign clk_o = en_latch & clk_i;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T23
0	1	Covered	T4,T24,T26
1	0	Covered	T4,T5,T6

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	22	2	2	100.00

22             if (!clk_i) begin
               -1-  
23               en_latch = en_i | test_en_i;
                 ==>
24             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	22	2	2	100.00
CONT_ASSIGN	26	1	1	100.00

21                        always_latch begin
22         1/1              if (!clk_i) begin
           Tests:       T4 T5 T6 
23         1/1                en_latch = en_i | test_en_i;
           Tests:       T4 T5 T6 
24                          end
                        MISSING_ELSE
25                        end
26         1/1            assign clk_o = en_latch & clk_i;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T23
0	1	Covered	T4,T24,T26
1	0	Covered	T4,T5,T6

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	22	2	2	100.00

22             if (!clk_i) begin
               -1-  
23               en_latch = en_i | test_en_i;
                 ==>
24             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	22	2	2	100.00
CONT_ASSIGN	26	1	1	100.00

21                        always_latch begin
22         1/1              if (!clk_i) begin
           Tests:       T4 T5 T6 
23         1/1                en_latch = en_i | test_en_i;
           Tests:       T4 T5 T6 
24                          end
                        MISSING_ELSE
25                        end
26         1/1            assign clk_o = en_latch & clk_i;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_usb_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T23
0	1	Covered	T4,T24,T26
1	0	Covered	T4,T5,T6

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_usb_root_ctrl.u_cg.i_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	22	2	2	100.00

22             if (!clk_i) begin
               -1-  
23               en_latch = en_i | test_en_i;
                 ==>
24             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	22	2	2	100.00
CONT_ASSIGN	26	1	1	100.00

21                        always_latch begin
22         1/1              if (!clk_i) begin
           Tests:       T4 T5 T6 
23         1/1                en_latch = en_i | test_en_i;
           Tests:       T4 T5 T6 
24                          end
                        MISSING_ELSE
25                        end
26         1/1            assign clk_o = en_latch & clk_i;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_clk_io_div4_peri_cg.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T23
0	1	Covered	T4,T24,T25
1	0	Covered	T4,T5,T6

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_clk_io_div4_peri_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	22	2	2	100.00

22             if (!clk_i) begin
               -1-  
23               en_latch = en_i | test_en_i;
                 ==>
24             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	22	2	2	100.00
CONT_ASSIGN	26	1	1	100.00

21                        always_latch begin
22         1/1              if (!clk_i) begin
           Tests:       T4 T5 T6 
23         1/1                en_latch = en_i | test_en_i;
           Tests:       T4 T5 T6 
24                          end
                        MISSING_ELSE
25                        end
26         1/1            assign clk_o = en_latch & clk_i;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_clk_io_div2_peri_cg.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T23
0	1	Covered	T4,T24,T25
1	0	Covered	T4,T5,T6

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_clk_io_div2_peri_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	22	2	2	100.00

22             if (!clk_i) begin
               -1-  
23               en_latch = en_i | test_en_i;
                 ==>
24             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_clk_io_peri_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	22	2	2	100.00
CONT_ASSIGN	26	1	1	100.00

21                        always_latch begin
22         1/1              if (!clk_i) begin
           Tests:       T4 T5 T6 
23         1/1                en_latch = en_i | test_en_i;
           Tests:       T4 T5 T6 
24                          end
                        MISSING_ELSE
25                        end
26         1/1            assign clk_o = en_latch & clk_i;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_clk_io_peri_cg.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T23
0	1	Covered	T4,T24,T25
1	0	Covered	T4,T5,T6

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_clk_io_peri_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	22	2	2	100.00

22             if (!clk_i) begin
               -1-  
23               en_latch = en_i | test_en_i;
                 ==>
24             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_clk_usb_peri_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	22	2	2	100.00
CONT_ASSIGN	26	1	1	100.00

21                        always_latch begin
22         1/1              if (!clk_i) begin
           Tests:       T4 T5 T6 
23         1/1                en_latch = en_i | test_en_i;
           Tests:       T4 T5 T6 
24                          end
                        MISSING_ELSE
25                        end
26         1/1            assign clk_o = en_latch & clk_i;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_clk_usb_peri_cg.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T23
0	1	Covered	T4,T24,T25
1	0	Covered	T4,T5,T6

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_clk_usb_peri_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	22	2	2	100.00

22             if (!clk_i) begin
               -1-  
23               en_latch = en_i | test_en_i;
                 ==>
24             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	22	2	2	100.00
CONT_ASSIGN	26	1	1	100.00

21                        always_latch begin
22         1/1              if (!clk_i) begin
           Tests:       T4 T5 T6 
23         1/1                en_latch = en_i | test_en_i;
           Tests:       T4 T5 T6 
24                          end
                        MISSING_ELSE
25                        end
26         1/1            assign clk_o = en_latch & clk_i;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_cg.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T27,T29
0	1	Covered	T27,T29,T88
1	0	Covered	T4,T5,T6

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T29
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	22	2	2	100.00

22             if (!clk_i) begin
               -1-  
23               en_latch = en_i | test_en_i;
                 ==>
24             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	22	2	2	100.00
CONT_ASSIGN	26	1	1	100.00

21                        always_latch begin
22         1/1              if (!clk_i) begin
           Tests:       T4 T5 T6 
23         1/1                en_latch = en_i | test_en_i;
           Tests:       T4 T5 T6 
24                          end
                        MISSING_ELSE
25                        end
26         1/1            assign clk_o = en_latch & clk_i;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_cg.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T27,T29
0	1	Covered	T27,T29,T88
1	0	Covered	T4,T5,T6

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T29
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	22	2	2	100.00

22             if (!clk_i) begin
               -1-  
23               en_latch = en_i | test_en_i;
                 ==>
24             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	22	2	2	100.00
CONT_ASSIGN	26	1	1	100.00

21                        always_latch begin
22         1/1              if (!clk_i) begin
           Tests:       T4 T5 T6 
23         1/1                en_latch = en_i | test_en_i;
           Tests:       T4 T5 T6 
24                          end
                        MISSING_ELSE
25                        end
26         1/1            assign clk_o = en_latch & clk_i;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_cg.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T27,T29
0	1	Covered	T27,T29,T88
1	0	Covered	T4,T5,T6

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T29
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	22	2	2	100.00

22             if (!clk_i) begin
               -1-  
23               en_latch = en_i | test_en_i;
                 ==>
24             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	22	2	2	100.00
CONT_ASSIGN	26	1	1	100.00

21                        always_latch begin
22         1/1              if (!clk_i) begin
           Tests:       T4 T5 T6 
23         1/1                en_latch = en_i | test_en_i;
           Tests:       T4 T5 T6 
24                          end
                        MISSING_ELSE
25                        end
26         1/1            assign clk_o = en_latch & clk_i;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_cg.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (en_i | test_en_i)
             --1-   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T5,T27,T29
0	1	Covered	T27,T29,T88
1	0	Covered	T4,T5,T6

 LINE       26
 EXPRESSION (en_latch & clk_i)
             ----1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T29
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_cg.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	22	2	2	100.00

22             if (!clk_i) begin
               -1-  
23               en_latch = en_i | test_en_i;
                 ==>
24             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6