Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	37713929	484641	0	0
clk_enables_rd_A	37713929	8958	0	0
clk_hints_rd_A	37713929	8857	0	0
extclk_ctrl_rd_A	37713929	10853	0	0
extclk_ctrl_regwen_rd_A	37713929	7033	0	0
jitter_enable_rd_A	37713929	14605	0	0
jitter_regwen_rd_A	37713929	6869	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37713929	484641	0	0
T17	0	6336	0	0
T30	114794	3141	0	0
T39	949	0	0	0
T40	941	0	0	0
T54	0	587	0	0
T56	15171	0	0	0
T75	0	4033	0	0
T76	0	4240	0	0
T77	0	5813	0	0
T78	0	5034	0	0
T79	0	10026	0	0
T80	0	9388	0	0
T81	0	2702	0	0
T82	1582	0	0	0
T83	1554	0	0	0
T84	2512	0	0	0
T85	2560	0	0	0
T86	1539	0	0	0
T87	1485	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37713929	8958	0	0
T5	2501	1	0	0
T6	1729	0	0	0
T17	0	233	0	0
T23	1197	0	0	0
T24	1548	0	0	0
T25	761	0	0	0
T26	1782	0	0	0
T27	2745	0	0	0
T28	1200	0	0	0
T29	3218	0	0	0
T30	0	186	0	0
T32	0	8	0	0
T42	0	6	0	0
T54	0	68	0	0
T55	1070	0	0	0
T75	0	185	0	0
T149	0	7	0	0
T150	0	6	0	0
T151	0	1	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37713929	8857	0	0
T5	2501	2	0	0
T6	1729	0	0	0
T17	0	204	0	0
T23	1197	0	0	0
T24	1548	0	0	0
T25	761	0	0	0
T26	1782	0	0	0
T27	2745	0	0	0
T28	1200	0	0	0
T29	3218	0	0	0
T30	0	130	0	0
T32	0	14	0	0
T47	0	9	0	0
T54	0	37	0	0
T55	1070	0	0	0
T149	0	14	0	0
T150	0	10	0	0
T152	0	4	0	0
T153	0	9	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37713929	10853	0	0
T2	0	52	0	0
T21	0	153	0	0
T30	0	217	0	0
T32	0	63	0	0
T44	8850	0	0	0
T45	1139	0	0	0
T47	2107	0	0	0
T49	1915	0	0	0
T58	2393	84	0	0
T82	0	48	0	0
T90	0	25	0	0
T101	2666	64	0	0
T102	1737	0	0	0
T114	2666	0	0	0
T126	1959	41	0	0
T127	1391	0	0	0
T154	0	20	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37713929	7033	0	0
T2	47890	15	0	0
T3	82618	0	0	0
T9	73435	0	0	0
T10	54943	0	0	0
T17	0	232	0	0
T20	54130	0	0	0
T21	111501	72	0	0
T22	129535	0	0	0
T30	0	133	0	0
T32	73744	0	0	0
T36	206209	0	0	0
T37	1113	0	0	0
T54	0	53	0	0
T75	0	148	0	0
T76	0	176	0	0
T155	0	53	0	0
T156	0	52	0	0
T157	0	6	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37713929	14605	0	0
T5	2501	117	0	0
T6	1729	0	0	0
T17	0	432	0	0
T23	1197	0	0	0
T24	1548	0	0	0
T25	761	0	0	0
T26	1782	0	0	0
T27	2745	0	0	0
T28	1200	0	0	0
T29	3218	0	0	0
T30	0	231	0	0
T32	0	242	0	0
T47	0	110	0	0
T54	0	35	0	0
T55	1070	0	0	0
T149	0	335	0	0
T150	0	104	0	0
T152	0	49	0	0
T153	0	129	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37713929	6869	0	0
T17	0	283	0	0
T30	114794	117	0	0
T39	949	0	0	0
T40	941	0	0	0
T54	0	72	0	0
T56	15171	0	0	0
T75	0	185	0	0
T76	0	179	0	0
T81	0	135	0	0
T82	1582	0	0	0
T83	1554	0	0	0
T84	2512	0	0	0
T85	2560	0	0	0
T86	1539	0	0	0
T87	1485	0	0	0
T158	0	162	0	0
T159	0	652	0	0
T160	0	569	0	0
T161	0	394	0	0