Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

24                        logic step_down;
25         1/1            always_comb step_down = div_step_down_req_i && !scanmode;
           Tests:       T4 T6 T24 
26                      
27                        logic step_up;
28         1/1            always_comb step_up = !step_down;
           Tests:       T4 T6 T24 

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T24
1	0	Covered	T6,T26,T101
1	1	Covered	T4,T6,T24

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	82314562	2536	0	0
g_div2.Div2Whole_A	82314562	3003	0	0
g_div4.Div4Stepped_A	40138681	2485	0	0
g_div4.Div4Whole_A	40138681	2829	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82314562	2536	0	0
T4	1844	4	0	0
T5	2449	0	0	0
T6	1712	4	0	0
T23	3941	0	0	0
T24	1487	0	0	0
T25	10440	0	0	0
T26	1746	4	0	0
T27	2774	0	0	0
T28	4114	0	0	0
T29	3090	0	0	0
T55	0	3	0	0
T58	0	5	0	0
T59	0	5	0	0
T101	0	4	0	0
T102	0	5	0	0
T114	0	8	0	0
T126	0	4	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82314562	3003	0	0
T4	1844	5	0	0
T5	2449	0	0	0
T6	1712	5	0	0
T23	3941	0	0	0
T24	1487	2	0	0
T25	10440	0	0	0
T26	1746	5	0	0
T27	2774	0	0	0
T28	4114	0	0	0
T29	3090	0	0	0
T55	0	3	0	0
T58	0	7	0	0
T101	0	6	0	0
T102	0	6	0	0
T114	0	9	0	0
T126	0	7	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40138681	2485	0	0
T4	927	4	0	0
T5	1185	0	0	0
T6	901	4	0	0
T23	1931	0	0	0
T24	711	0	0	0
T25	5153	0	0	0
T26	876	4	0	0
T27	1361	0	0	0
T28	2031	0	0	0
T29	1513	0	0	0
T55	0	3	0	0
T58	0	3	0	0
T59	0	5	0	0
T101	0	4	0	0
T102	0	4	0	0
T114	0	6	0	0
T126	0	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40138681	2829	0	0
T4	927	4	0	0
T5	1185	0	0	0
T6	901	5	0	0
T23	1931	0	0	0
T24	711	2	0	0
T25	5153	0	0	0
T26	876	5	0	0
T27	1361	0	0	0
T28	2031	0	0	0
T29	1513	0	0	0
T55	0	3	0	0
T58	0	6	0	0
T101	0	6	0	0
T102	0	4	0	0
T114	0	8	0	0
T126	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

24                        logic step_down;
25         1/1            always_comb step_down = div_step_down_req_i && !scanmode;
           Tests:       T4 T6 T24 
26                      
27                        logic step_up;
28         1/1            always_comb step_up = !step_down;
           Tests:       T4 T6 T24 

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T24
1	0	Covered	T6,T26,T101
1	1	Covered	T4,T6,T24

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	82314562	2536	0	0
g_div2.Div2Whole_A	82314562	3003	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82314562	2536	0	0
T4	1844	4	0	0
T5	2449	0	0	0
T6	1712	4	0	0
T23	3941	0	0	0
T24	1487	0	0	0
T25	10440	0	0	0
T26	1746	4	0	0
T27	2774	0	0	0
T28	4114	0	0	0
T29	3090	0	0	0
T55	0	3	0	0
T58	0	5	0	0
T59	0	5	0	0
T101	0	4	0	0
T102	0	5	0	0
T114	0	8	0	0
T126	0	4	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82314562	3003	0	0
T4	1844	5	0	0
T5	2449	0	0	0
T6	1712	5	0	0
T23	3941	0	0	0
T24	1487	2	0	0
T25	10440	0	0	0
T26	1746	5	0	0
T27	2774	0	0	0
T28	4114	0	0	0
T29	3090	0	0	0
T55	0	3	0	0
T58	0	7	0	0
T101	0	6	0	0
T102	0	6	0	0
T114	0	9	0	0
T126	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

24                        logic step_down;
25         1/1            always_comb step_down = div_step_down_req_i && !scanmode;
           Tests:       T4 T6 T24 
26                      
27                        logic step_up;
28         1/1            always_comb step_up = !step_down;
           Tests:       T4 T6 T24 

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T24
1	0	Covered	T6,T26,T101
1	1	Covered	T4,T6,T24

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	40138681	2485	0	0
g_div4.Div4Whole_A	40138681	2829	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40138681	2485	0	0
T4	927	4	0	0
T5	1185	0	0	0
T6	901	4	0	0
T23	1931	0	0	0
T24	711	0	0	0
T25	5153	0	0	0
T26	876	4	0	0
T27	1361	0	0	0
T28	2031	0	0	0
T29	1513	0	0	0
T55	0	3	0	0
T58	0	3	0	0
T59	0	5	0	0
T101	0	4	0	0
T102	0	4	0	0
T114	0	6	0	0
T126	0	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40138681	2829	0	0
T4	927	4	0	0
T5	1185	0	0	0
T6	901	5	0	0
T23	1931	0	0	0
T24	711	2	0	0
T25	5153	0	0	0
T26	876	5	0	0
T27	1361	0	0	0
T28	2031	0	0	0
T29	1513	0	0	0
T55	0	3	0	0
T58	0	6	0	0
T101	0	6	0	0
T102	0	4	0	0
T114	0	8	0	0
T126	0	7	0	0