Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	110248746	420	0	0
StatusRise_A	110248746	420	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110248746	420	0	0
T23	3591	14	0	0
T24	4644	0	0	0
T25	2283	0	0	0
T26	5346	0	0	0
T27	8235	0	0	0
T28	3600	0	0	0
T29	9654	0	0	0
T40	0	10	0	0
T45	0	8	0	0
T46	0	9	0	0
T55	3210	0	0	0
T88	7518	0	0	0
T89	4086	0	0	0
T162	0	14	0	0
T163	0	8	0	0
T164	0	13	0	0
T165	0	11	0	0
T166	0	3	0	0
T167	0	13	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	110248746	420	0	0
T23	3591	14	0	0
T24	4644	0	0	0
T25	2283	0	0	0
T26	5346	0	0	0
T27	8235	0	0	0
T28	3600	0	0	0
T29	9654	0	0	0
T40	0	10	0	0
T45	0	8	0	0
T46	0	9	0	0
T55	3210	0	0	0
T88	7518	0	0	0
T89	4086	0	0	0
T162	0	14	0	0
T163	0	8	0	0
T164	0	13	0	0
T165	0	11	0	0
T166	0	3	0	0
T167	0	13	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	36749582	134	0	0
StatusRise_A	36749582	134	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	134	0	0
T23	1197	4	0	0
T24	1548	0	0	0
T25	761	0	0	0
T26	1782	0	0	0
T27	2745	0	0	0
T28	1200	0	0	0
T29	3218	0	0	0
T40	0	3	0	0
T45	0	3	0	0
T46	0	3	0	0
T55	1070	0	0	0
T88	2506	0	0	0
T89	1362	0	0	0
T162	0	4	0	0
T163	0	2	0	0
T164	0	3	0	0
T165	0	5	0	0
T166	0	1	0	0
T167	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	134	0	0
T23	1197	4	0	0
T24	1548	0	0	0
T25	761	0	0	0
T26	1782	0	0	0
T27	2745	0	0	0
T28	1200	0	0	0
T29	3218	0	0	0
T40	0	3	0	0
T45	0	3	0	0
T46	0	3	0	0
T55	1070	0	0	0
T88	2506	0	0	0
T89	1362	0	0	0
T162	0	4	0	0
T163	0	2	0	0
T164	0	3	0	0
T165	0	5	0	0
T166	0	1	0	0
T167	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	36749582	145	0	0
StatusRise_A	36749582	145	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	145	0	0
T23	1197	5	0	0
T24	1548	0	0	0
T25	761	0	0	0
T26	1782	0	0	0
T27	2745	0	0	0
T28	1200	0	0	0
T29	3218	0	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T55	1070	0	0	0
T88	2506	0	0	0
T89	1362	0	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	0	4	0	0
T166	0	1	0	0
T167	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	145	0	0
T23	1197	5	0	0
T24	1548	0	0	0
T25	761	0	0	0
T26	1782	0	0	0
T27	2745	0	0	0
T28	1200	0	0	0
T29	3218	0	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T55	1070	0	0	0
T88	2506	0	0	0
T89	1362	0	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	0	4	0	0
T166	0	1	0	0
T167	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	36749582	141	0	0
StatusRise_A	36749582	141	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	141	0	0
T23	1197	5	0	0
T24	1548	0	0	0
T25	761	0	0	0
T26	1782	0	0	0
T27	2745	0	0	0
T28	1200	0	0	0
T29	3218	0	0	0
T40	0	5	0	0
T45	0	3	0	0
T46	0	3	0	0
T55	1070	0	0	0
T88	2506	0	0	0
T89	1362	0	0	0
T162	0	5	0	0
T163	0	4	0	0
T164	0	5	0	0
T165	0	2	0	0
T166	0	1	0	0
T167	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36749582	141	0	0
T23	1197	5	0	0
T24	1548	0	0	0
T25	761	0	0	0
T26	1782	0	0	0
T27	2745	0	0	0
T28	1200	0	0	0
T29	3218	0	0	0
T40	0	5	0	0
T45	0	3	0	0
T46	0	3	0	0
T55	1070	0	0	0
T88	2506	0	0	0
T89	1362	0	0	0
T162	0	5	0	0
T163	0	4	0	0
T164	0	5	0	0
T165	0	2	0	0
T166	0	1	0	0
T167	0	4	0	0