Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T44,T45
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	960217522	32027	0	0
CgEnOn_A	960217522	22830	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	960217522	32027	0	0
T4	4156	3	0	0
T5	15654	7	0	0
T6	11048	3	0	0
T23	44226	47	0	0
T24	16594	3	0	0
T25	117180	34	0	0
T26	19642	3	0	0
T27	31094	9	0	0
T28	46172	3	0	0
T29	34626	12	0	0
T40	0	10	0	0
T45	0	13	0	0
T46	0	15	0	0
T55	84852	0	0	0
T88	48306	5	0	0
T89	26309	4	0	0
T162	0	25	0	0
T163	0	10	0	0
T164	0	25	0	0
T165	0	20	0	0
T166	0	5	0	0
T167	0	25	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	960217522	22830	0	0
T5	15654	4	0	0
T6	11048	0	0	0
T23	44226	44	0	0
T24	16594	0	0	0
T25	117180	31	0	0
T26	19642	0	0	0
T27	31094	6	0	0
T28	46172	0	0	0
T29	34626	9	0	0
T32	0	12	0	0
T40	0	10	0	0
T45	0	19	0	0
T46	0	24	0	0
T47	0	4	0	0
T48	0	4	0	0
T55	106346	0	0	0
T60	0	9	0	0
T74	0	29	0	0
T88	48306	5	0	0
T89	26309	4	0	0
T162	0	25	0	0
T163	0	10	0	0
T164	0	25	0	0
T165	0	20	0	0
T166	0	5	0	0
T167	0	25	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T44,T45
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	40138291	163	0	0
CgEnOn_A	40138291	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40138291	163	0	0
T23	1931	5	0	0
T24	711	0	0	0
T25	5153	0	0	0
T26	875	0	0	0
T27	1361	0	0	0
T28	2031	0	0	0
T29	1512	0	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T55	4990	0	0	0
T88	4947	0	0	0
T89	2708	0	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	0	4	0	0
T166	0	1	0	0
T167	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40138291	163	0	0
T23	1931	5	0	0
T24	711	0	0	0
T25	5153	0	0	0
T26	875	0	0	0
T27	1361	0	0	0
T28	2031	0	0	0
T29	1512	0	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T55	4990	0	0	0
T88	4947	0	0	0
T89	2708	0	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	0	4	0	0
T166	0	1	0	0
T167	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T44,T45
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	20068807	163	0	0
CgEnOn_A	20068807	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20068807	163	0	0
T23	965	5	0	0
T24	356	0	0	0
T25	2576	0	0	0
T26	437	0	0	0
T27	680	0	0	0
T28	1015	0	0	0
T29	756	0	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T55	2495	0	0	0
T88	2474	0	0	0
T89	1354	0	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	0	4	0	0
T166	0	1	0	0
T167	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20068807	163	0	0
T23	965	5	0	0
T24	356	0	0	0
T25	2576	0	0	0
T26	437	0	0	0
T27	680	0	0	0
T28	1015	0	0	0
T29	756	0	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T55	2495	0	0	0
T88	2474	0	0	0
T89	1354	0	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	0	4	0	0
T166	0	1	0	0
T167	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T44,T45
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	20068807	163	0	0
CgEnOn_A	20068807	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20068807	163	0	0
T23	965	5	0	0
T24	356	0	0	0
T25	2576	0	0	0
T26	437	0	0	0
T27	680	0	0	0
T28	1015	0	0	0
T29	756	0	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T55	2495	0	0	0
T88	2474	0	0	0
T89	1354	0	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	0	4	0	0
T166	0	1	0	0
T167	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20068807	163	0	0
T23	965	5	0	0
T24	356	0	0	0
T25	2576	0	0	0
T26	437	0	0	0
T27	680	0	0	0
T28	1015	0	0	0
T29	756	0	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T55	2495	0	0	0
T88	2474	0	0	0
T89	1354	0	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	0	4	0	0
T166	0	1	0	0
T167	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T44,T45
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	20068807	163	0	0
CgEnOn_A	20068807	163	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20068807	163	0	0
T23	965	5	0	0
T24	356	0	0	0
T25	2576	0	0	0
T26	437	0	0	0
T27	680	0	0	0
T28	1015	0	0	0
T29	756	0	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T55	2495	0	0	0
T88	2474	0	0	0
T89	1354	0	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	0	4	0	0
T166	0	1	0	0
T167	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20068807	163	0	0
T23	965	5	0	0
T24	356	0	0	0
T25	2576	0	0	0
T26	437	0	0	0
T27	680	0	0	0
T28	1015	0	0	0
T29	756	0	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T55	2495	0	0	0
T88	2474	0	0	0
T89	1354	0	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	0	4	0	0
T166	0	1	0	0
T167	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T44,T45
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	82314126	163	0	0
CgEnOn_A	82314126	148	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82314126	163	0	0
T23	3941	5	0	0
T24	1487	0	0	0
T25	10440	0	0	0
T26	1745	0	0	0
T27	2773	0	0	0
T28	4113	0	0	0
T29	3090	0	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T55	9339	0	0	0
T88	10029	0	0	0
T89	5453	0	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	0	4	0	0
T166	0	1	0	0
T167	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82314126	148	0	0
T23	3941	5	0	0
T24	1487	0	0	0
T25	10440	0	0	0
T26	1745	0	0	0
T27	2773	0	0	0
T28	4113	0	0	0
T29	3090	0	0	0
T40	0	2	0	0
T45	0	2	0	0
T46	0	3	0	0
T55	9339	0	0	0
T88	10029	0	0	0
T89	5453	0	0	0
T162	0	5	0	0
T163	0	2	0	0
T164	0	5	0	0
T165	0	4	0	0
T166	0	1	0	0
T167	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T44,T45
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91230460	141	0	0
CgEnOn_A	91230460	136	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230460	141	0	0
T23	4109	4	0	0
T24	1548	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	0	0	0
T28	4285	0	0	0
T29	3218	0	0	0
T40	0	3	0	0
T45	0	3	0	0
T46	0	3	0	0
T55	9728	0	0	0
T88	10447	0	0	0
T89	5680	0	0	0
T162	0	4	0	0
T163	0	2	0	0
T164	0	3	0	0
T165	0	5	0	0
T166	0	1	0	0
T167	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230460	136	0	0
T23	4109	4	0	0
T24	1548	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	0	0	0
T28	4285	0	0	0
T29	3218	0	0	0
T40	0	3	0	0
T45	0	3	0	0
T46	0	3	0	0
T55	9728	0	0	0
T88	10447	0	0	0
T89	5680	0	0	0
T162	0	4	0	0
T163	0	2	0	0
T164	0	3	0	0
T165	0	5	0	0
T166	0	1	0	0
T167	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T44,T45
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91230460	141	0	0
CgEnOn_A	91230460	136	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230460	141	0	0
T23	4109	4	0	0
T24	1548	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	0	0	0
T28	4285	0	0	0
T29	3218	0	0	0
T40	0	3	0	0
T45	0	3	0	0
T46	0	3	0	0
T55	9728	0	0	0
T88	10447	0	0	0
T89	5680	0	0	0
T162	0	4	0	0
T163	0	2	0	0
T164	0	3	0	0
T165	0	5	0	0
T166	0	1	0	0
T167	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230460	136	0	0
T23	4109	4	0	0
T24	1548	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	0	0	0
T28	4285	0	0	0
T29	3218	0	0	0
T40	0	3	0	0
T45	0	3	0	0
T46	0	3	0	0
T55	9728	0	0	0
T88	10447	0	0	0
T89	5680	0	0	0
T162	0	4	0	0
T163	0	2	0	0
T164	0	3	0	0
T165	0	5	0	0
T166	0	1	0	0
T167	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T44,T45
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	43827350	144	0	0
CgEnOn_A	43827350	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43827350	144	0	0
T23	1984	5	0	0
T24	743	0	0	0
T25	5220	0	0	0
T26	873	0	0	0
T27	1386	0	0	0
T28	2057	0	0	0
T29	1545	0	0	0
T40	0	5	0	0
T45	0	3	0	0
T46	0	3	0	0
T55	4670	0	0	0
T88	5014	0	0	0
T89	2726	0	0	0
T162	0	5	0	0
T163	0	4	0	0
T164	0	5	0	0
T165	0	2	0	0
T166	0	1	0	0
T167	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43827350	141	0	0
T23	1984	5	0	0
T24	743	0	0	0
T25	5220	0	0	0
T26	873	0	0	0
T27	1386	0	0	0
T28	2057	0	0	0
T29	1545	0	0	0
T40	0	5	0	0
T45	0	3	0	0
T46	0	3	0	0
T55	4670	0	0	0
T88	5014	0	0	0
T89	2726	0	0	0
T162	0	5	0	0
T163	0	4	0	0
T164	0	5	0	0
T165	0	2	0	0
T166	0	1	0	0
T167	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T45,T46
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	20068807	5202	0	0
CgEnOn_A	20068807	2923	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20068807	5202	0	0
T4	463	1	0	0
T5	592	2	0	0
T6	450	1	0	0
T23	965	6	0	0
T24	356	1	0	0
T25	2576	11	0	0
T26	437	1	0	0
T27	680	1	0	0
T28	1015	1	0	0
T29	756	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20068807	2923	0	0
T5	592	1	0	0
T6	450	0	0	0
T23	965	5	0	0
T24	356	0	0	0
T25	2576	10	0	0
T26	437	0	0	0
T27	680	0	0	0
T28	1015	0	0	0
T29	756	0	0	0
T32	0	4	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	2495	0	0	0
T60	0	3	0	0
T74	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T45,T46
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	40138291	5226	0	0
CgEnOn_A	40138291	2947	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40138291	5226	0	0
T4	927	1	0	0
T5	1185	2	0	0
T6	900	1	0	0
T23	1931	6	0	0
T24	711	1	0	0
T25	5153	12	0	0
T26	875	1	0	0
T27	1361	1	0	0
T28	2031	1	0	0
T29	1512	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40138291	2947	0	0
T5	1185	1	0	0
T6	900	0	0	0
T23	1931	5	0	0
T24	711	0	0	0
T25	5153	11	0	0
T26	875	0	0	0
T27	1361	0	0	0
T28	2031	0	0	0
T29	1512	0	0	0
T32	0	4	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	4990	0	0	0
T60	0	3	0	0
T74	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T45,T46
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	82314126	5251	0	0
CgEnOn_A	82314126	2957	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82314126	5251	0	0
T4	1844	1	0	0
T5	2449	2	0	0
T6	1711	1	0	0
T23	3941	6	0	0
T24	1487	1	0	0
T25	10440	11	0	0
T26	1745	1	0	0
T27	2773	1	0	0
T28	4113	1	0	0
T29	3090	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82314126	2957	0	0
T5	2449	1	0	0
T6	1711	0	0	0
T23	3941	5	0	0
T24	1487	0	0	0
T25	10440	10	0	0
T26	1745	0	0	0
T27	2773	0	0	0
T28	4113	0	0	0
T29	3090	0	0	0
T32	0	4	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9339	0	0	0
T60	0	3	0	0
T74	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T45,T46
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	43827350	5223	0	0
CgEnOn_A	43827350	2926	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43827350	5223	0	0
T4	922	1	0	0
T5	1224	2	0	0
T6	855	1	0	0
T23	1984	6	0	0
T24	743	1	0	0
T25	5220	12	0	0
T26	873	1	0	0
T27	1386	1	0	0
T28	2057	1	0	0
T29	1545	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43827350	2926	0	0
T5	1224	1	0	0
T6	855	0	0	0
T23	1984	5	0	0
T24	743	0	0	0
T25	5220	11	0	0
T26	873	0	0	0
T27	1386	0	0	0
T28	2057	0	0	0
T29	1545	0	0	0
T32	0	4	0	0
T45	0	3	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	4670	0	0	0
T60	0	3	0	0
T74	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T44,T45
1	0	Covered	T5,T27,T29
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91230460	2431	0	0
CgEnOn_A	91230460	2426	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230460	2431	0	0
T5	2551	1	0	0
T6	1783	0	0	0
T23	4109	4	0	0
T24	1548	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	6	0	0
T28	4285	0	0	0
T29	3218	9	0	0
T45	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9728	0	0	0
T88	0	5	0	0
T89	0	4	0	0
T127	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230460	2426	0	0
T5	2551	1	0	0
T6	1783	0	0	0
T23	4109	4	0	0
T24	1548	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	6	0	0
T28	4285	0	0	0
T29	3218	9	0	0
T45	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9728	0	0	0
T88	0	5	0	0
T89	0	4	0	0
T127	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T44,T45
1	0	Covered	T5,T27,T29
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91230460	2455	0	0
CgEnOn_A	91230460	2450	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230460	2455	0	0
T5	2551	1	0	0
T6	1783	0	0	0
T23	4109	4	0	0
T24	1548	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	4	0	0
T28	4285	0	0	0
T29	3218	9	0	0
T45	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9728	0	0	0
T88	0	7	0	0
T89	0	5	0	0
T127	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230460	2450	0	0
T5	2551	1	0	0
T6	1783	0	0	0
T23	4109	4	0	0
T24	1548	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	4	0	0
T28	4285	0	0	0
T29	3218	9	0	0
T45	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9728	0	0	0
T88	0	7	0	0
T89	0	5	0	0
T127	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T44,T45
1	0	Covered	T5,T27,T29
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91230460	2462	0	0
CgEnOn_A	91230460	2457	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230460	2462	0	0
T5	2551	1	0	0
T6	1783	0	0	0
T23	4109	4	0	0
T24	1548	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	8	0	0
T28	4285	0	0	0
T29	3218	5	0	0
T45	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9728	0	0	0
T88	0	7	0	0
T89	0	4	0	0
T127	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230460	2457	0	0
T5	2551	1	0	0
T6	1783	0	0	0
T23	4109	4	0	0
T24	1548	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	8	0	0
T28	4285	0	0	0
T29	3218	5	0	0
T45	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9728	0	0	0
T88	0	7	0	0
T89	0	4	0	0
T127	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T23,T44,T45
1	0	Covered	T5,T27,T29
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	91230460	2536	0	0
CgEnOn_A	91230460	2531	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230460	2536	0	0
T5	2551	1	0	0
T6	1783	0	0	0
T23	4109	4	0	0
T24	1548	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	8	0	0
T28	4285	0	0	0
T29	3218	10	0	0
T45	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9728	0	0	0
T88	0	8	0	0
T89	0	5	0	0
T127	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91230460	2531	0	0
T5	2551	1	0	0
T6	1783	0	0	0
T23	4109	4	0	0
T24	1548	0	0	0
T25	10875	0	0	0
T26	1818	0	0	0
T27	2889	8	0	0
T28	4285	0	0	0
T29	3218	10	0	0
T45	0	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	9728	0	0	0
T88	0	8	0	0
T89	0	5	0	0
T127	0	2	0	0