Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	203197	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

496961

1

T4

28

T5

14

T29

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	202544	1			T4	42		T5	12		T29	8
values[0x0]	236109	1			T4	24		T5	11		T29	4
values[0x1]	261505	1			T4	15		T5	14		T6	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	141079	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

559079

1

T4

36

T5

18

T6

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3477	1			T43	1		T3	15		T25	4
valid_sources[0x01]	2487	1			T2	1		T44	1		T47	1
valid_sources[0x02]	2731	1			T59	1		T3	1		T49	2
valid_sources[0x03]	2361	1			T32	2		T11	7		T184	70
valid_sources[0x04]	2520	1			T4	2		T47	1		T3	22
valid_sources[0x05]	3382	1			T47	1		T20	3		T11	4
valid_sources[0x06]	2608	1			T37	2		T44	1		T3	15
valid_sources[0x07]	3746	1			T45	1		T61	2		T3	10
valid_sources[0x08]	2614	1			T49	1		T20	1		T23	9
valid_sources[0x09]	2573	1			T37	12		T45	1		T49	1
valid_sources[0x0a]	2542	1			T1	1		T3	23		T98	1
valid_sources[0x0b]	2616	1			T31	2		T44	1		T23	1
valid_sources[0x0c]	2251	1			T45	1		T3	8		T11	2
valid_sources[0x0d]	2436	1			T44	3		T3	5		T24	2
valid_sources[0x0e]	2246	1			T23	1		T11	4		T149	2
valid_sources[0x0f]	2495	1			T20	1		T24	5		T11	8
valid_sources[0x10]	2702	1			T2	1		T44	1		T45	1
valid_sources[0x11]	5002	1			T44	1		T51	3		T20	1
valid_sources[0x12]	2914	1			T45	1		T61	2		T20	1
valid_sources[0x13]	3357	1			T2	3		T38	39		T20	2
valid_sources[0x14]	3133	1			T49	1		T20	1		T23	1
valid_sources[0x15]	2258	1			T47	1		T28	2		T97	4
valid_sources[0x16]	2565	1			T59	1		T3	10		T51	6
valid_sources[0x17]	2027	1			T44	1		T47	1		T59	1
valid_sources[0x18]	2568	1			T5	4		T44	1		T96	1
valid_sources[0x19]	2191	1			T31	1		T2	2		T43	1
valid_sources[0x1a]	2263	1			T3	5		T28	1		T11	5
valid_sources[0x1b]	2775	1			T4	7		T1	2		T47	1
valid_sources[0x1c]	2545	1			T47	1		T3	1		T20	2
valid_sources[0x1d]	2356	1			T45	1		T3	12		T49	1
valid_sources[0x1e]	2867	1			T3	5		T49	3		T20	3
valid_sources[0x1f]	2377	1			T31	2		T44	1		T59	1
valid_sources[0x20]	2527	1			T1	1		T3	7		T11	4
valid_sources[0x21]	2698	1			T5	1		T31	1		T47	1
valid_sources[0x22]	2676	1			T1	1		T59	1		T96	1
valid_sources[0x23]	2538	1			T3	8		T49	1		T28	1
valid_sources[0x24]	3928	1			T2	1		T45	1		T3	10
valid_sources[0x25]	2780	1			T1	1		T45	1		T38	72
valid_sources[0x26]	3621	1			T44	2		T59	2		T98	1
valid_sources[0x27]	2468	1			T1	1		T2	3		T45	1
valid_sources[0x28]	2500	1			T49	2		T97	3		T11	5
valid_sources[0x29]	2509	1			T2	1		T45	1		T3	36
valid_sources[0x2a]	2171	1			T44	1		T45	1		T98	1
valid_sources[0x2b]	2597	1			T4	37		T2	1		T59	1
valid_sources[0x2c]	2726	1			T44	1		T47	1		T3	2
valid_sources[0x2d]	2592	1			T44	2		T47	2		T59	1
valid_sources[0x2e]	2645	1			T1	1		T45	1		T59	1
valid_sources[0x2f]	2474	1			T1	4		T44	1		T98	1
valid_sources[0x30]	2996	1			T32	2		T49	1		T23	1
valid_sources[0x31]	3601	1			T2	2		T44	1		T61	1
valid_sources[0x32]	2598	1			T44	1		T3	13		T49	1
valid_sources[0x33]	3249	1			T2	1		T47	1		T61	1
valid_sources[0x34]	2293	1			T45	1		T3	15		T49	1
valid_sources[0x35]	2665	1			T59	1		T38	19		T20	1
valid_sources[0x36]	3596	1			T47	1		T49	2		T11	5
valid_sources[0x37]	4721	1			T2	1		T44	1		T3	17
valid_sources[0x38]	2323	1			T47	1		T3	1		T24	3
valid_sources[0x39]	2702	1			T28	1		T97	2		T11	3
valid_sources[0x3a]	2503	1			T2	2		T11	7		T155	1
valid_sources[0x3b]	2497	1			T44	1		T62	25		T3	7
valid_sources[0x3c]	3029	1			T37	4		T44	1		T47	1
valid_sources[0x3d]	2490	1			T2	1		T45	1		T3	9
valid_sources[0x3e]	2826	1			T1	1		T44	1		T47	1
valid_sources[0x3f]	2861	1			T43	1		T44	1		T47	1
valid_sources[0x40]	3496	1			T47	1		T96	2		T11	5
valid_sources[0x41]	2356	1			T4	8		T97	2		T11	8
valid_sources[0x42]	2892	1			T6	1		T47	3		T59	1
valid_sources[0x43]	2724	1			T31	4		T47	1		T51	1
valid_sources[0x44]	3707	1			T31	1		T43	1		T45	1
valid_sources[0x45]	2665	1			T2	2		T44	1		T59	1
valid_sources[0x46]	2524	1			T44	1		T45	1		T47	1
valid_sources[0x47]	2481	1			T5	8		T42	5		T45	1
valid_sources[0x48]	4252	1			T44	3		T47	1		T59	1
valid_sources[0x49]	2410	1			T37	5		T38	10		T11	6
valid_sources[0x4a]	2164	1			T49	3		T23	2		T96	1
valid_sources[0x4b]	2269	1			T4	2		T43	1		T60	1
valid_sources[0x4c]	3236	1			T43	1		T59	2		T49	1
valid_sources[0x4d]	2600	1			T38	10		T11	4		T149	5
valid_sources[0x4e]	2637	1			T2	1		T59	2		T49	1
valid_sources[0x4f]	2526	1			T46	2		T49	1		T95	14
valid_sources[0x50]	2539	1			T45	1		T47	1		T20	1
valid_sources[0x51]	3097	1			T28	3		T97	1		T11	3
valid_sources[0x52]	2592	1			T44	1		T45	1		T3	1
valid_sources[0x53]	2908	1			T59	1		T49	1		T11	6
valid_sources[0x54]	2949	1			T5	4		T20	1		T97	2
valid_sources[0x55]	3293	1			T1	1		T47	1		T28	1
valid_sources[0x56]	2701	1			T2	2		T20	1		T11	4
valid_sources[0x57]	2381	1			T11	6		T111	1		T57	1
valid_sources[0x58]	3153	1			T1	1		T3	6		T20	4
valid_sources[0x59]	2673	1			T3	5		T38	15		T52	8
valid_sources[0x5a]	2612	1			T97	7		T98	1		T11	2
valid_sources[0x5b]	3113	1			T1	3		T2	1		T20	1
valid_sources[0x5c]	2326	1			T31	1		T44	1		T45	1
valid_sources[0x5d]	2838	1			T1	1		T60	1		T3	14
valid_sources[0x5e]	2334	1			T94	32		T97	2		T11	4
valid_sources[0x5f]	1902	1			T1	1		T47	1		T3	1
valid_sources[0x60]	2821	1			T43	1		T96	2		T11	4
valid_sources[0x61]	2407	1			T1	1		T59	3		T20	1
valid_sources[0x62]	3404	1			T1	1		T45	2		T49	1
valid_sources[0x63]	3020	1			T43	1		T49	1		T28	1
valid_sources[0x64]	3026	1			T44	1		T11	5		T150	2
valid_sources[0x65]	3334	1			T5	7		T45	1		T3	15
valid_sources[0x66]	3020	1			T31	3		T1	1		T47	1
valid_sources[0x67]	2539	1			T31	8		T3	9		T24	2
valid_sources[0x68]	2289	1			T2	1		T3	11		T96	1
valid_sources[0x69]	2805	1			T44	1		T3	4		T49	1
valid_sources[0x6a]	2288	1			T47	1		T3	4		T49	1
valid_sources[0x6b]	2243	1			T60	2		T61	2		T49	1
valid_sources[0x6c]	2861	1			T47	1		T61	2		T20	1
valid_sources[0x6d]	2957	1			T59	2		T49	1		T10	384
valid_sources[0x6e]	2743	1			T59	1		T27	14		T11	6
valid_sources[0x6f]	2835	1			T2	2		T47	1		T28	3
valid_sources[0x70]	2512	1			T45	1		T3	4		T96	1
valid_sources[0x71]	2792	1			T37	13		T44	1		T47	2
valid_sources[0x72]	2545	1			T47	1		T49	1		T20	1
valid_sources[0x73]	3096	1			T33	1		T44	1		T47	1
valid_sources[0x74]	2337	1			T47	2		T96	2		T11	4
valid_sources[0x75]	2842	1			T43	1		T44	1		T45	1
valid_sources[0x76]	2710	1			T45	1		T47	2		T20	3
valid_sources[0x77]	2806	1			T2	1		T3	5		T20	1
valid_sources[0x78]	2702	1			T44	1		T45	1		T97	4
valid_sources[0x79]	2746	1			T29	14		T31	5		T2	3
valid_sources[0x7a]	2813	1			T45	1		T11	3		T149	2
valid_sources[0x7b]	2317	1			T47	2		T59	2		T3	11
valid_sources[0x7c]	5266	1			T44	1		T20	3		T98	1
valid_sources[0x7d]	2694	1			T31	4		T34	10		T44	1
valid_sources[0x7e]	2764	1			T44	1		T97	2		T11	4
valid_sources[0x7f]	3243	1			T1	1		T44	1		T47	1
valid_sources[0x80]	2140	1			T1	1		T11	2		T35	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

138102

1

T4

17

T5

9

T29

3

values[0x0]

all_enables

biggest_size

191896

1

T4

7

T5

2

T29

3

values[0x1]

all_enables

biggest_size

166963

1

T4

4

T5

3

T31

2